MOSFET and Memory Cell Having Improved Drain Current Through Back Bias Application

ABSTRACT

A semiconductor metal-oxide-semiconductor field effect transistor (MOSFET) transistor with increased on-state current obtained through intrinsic bipolar junction transistor (BJT) of MOSFET has been described. Methods of operating the MOS transistor are provided.

FIELD OF THE INVENTION

This invention relates to semiconductor metal-oxide-semiconductor field effect transistor (MOSFET) transistor with increased on-state current obtained through bipolar junction transistor (BJT) of MOSFET and semiconductor non-volatile memory cell having reduced operating voltage by utilizing inherent bipolar junction transistor (BJT). More particularly, the on-state drain current is increased due to the turned-on BJT when the MOSFET is turned on but the off-state drain current is unchanged due to the turned-off BJT when the MOSFET is turned off.

BACKGROUND OF THE INVENTION

Because PN junctions are created in source-to-channel and the drain-to-channel of a MOSFET, a BJT is inherently formed during manufacture of the MOSFET. The inherent BJT is connected in parallel to the MOSFET, where emitter, base, and collector of the BJT are formed from the source, channel, and drain of the MOSFET, respectively. The n-channel MOSFET would have npn-type BJT and the p-channel MOSFET would have pnp-type BJT.

In a conventional MOSFET, the intrinsic BJT rarely contributes to the drain current. Currently, the manufacturing process and operation scheme for MOSFETs are designed to nullify the effect of the inherent BJT. Clearly, a manufacturing process and operation scheme that would utilize the inherent BJT to enhance the MOSFET performance would be desirable.

SUMMARY OF THE INVENTION

A semiconductor device structure to increase on-state drain current but the off-state drain current is unchanged. A non-volatile memory cell having reduced operating voltage by utilizing inherent BJT is also disclosed. Methods of operating the semiconductor device and non-volatile memory cell are provided.

In one aspect of the present invention, a semiconductor device configured to function as a semiconductor memory device or a transistor with increased on-state drain current, includes a substrate having a first conductivity type selected from p-type conductivity type and n-type conductivity type; a buried layer having a second conductivity type selected from the p-type conductivity type and the n-type conductivity type and being different from the first conductivity type; a body having the first conductivity type; a source region and a drain region each having the second conductivity type and being separated by the body; and a gate positioned in between the source region and the drain region; wherein the semiconductor device is configured to function as a memory device having at least two stable states, or as a transistor with increased on-state drain current, but with no change in off-state drain current, depending on biases that are applied to the semiconductor device.

In at least one embodiment, whether the semiconductor device functions as the memory device having at least two stable states, or as the transistor with increased on-state drain current, but with no change in off-state drain current is governed by an amount of voltage applied to the buried layer.

In at least one embodiment, a relatively low voltage applied to the buried layer governs the semiconductor device to function as a MOSFET (metal-oxide-semiconductor field effect transistor) and wherein a relatively high voltage applied to the buried layer governs the semiconductor device to function as the memory device having at least two stable states.

In at least one embodiment, a relatively intermediate high voltage applied to the buried layer higher than the relatively low voltage and lower than the relatively high voltage, but sufficient to turn on a vertical bipolar junction transistor (BJT) formed by the buried layer, the body and the source region, turns on a lateral BJT formed by the source region, the body and the drain region, resulting in increased on-state drain current.

In at least one embodiment, the on-state drain current comprises the sum of current from a MOS transistor formed by the source region, the gate and the drain region and current from the lateral BJT.

In at least one embodiment, the semiconductor device further includes a buried layer tap connected to the buried layer.

In at least one embodiment, the buried layer tap has the second conductivity type.

In at least one embodiment, the buried layer, the body, the source region, the drain region and the gate comprise a first buried layer, a first body, a first source region, a first drain region and a first gate, respectively, the semiconductor device further comprising: a well formed in the substrate and having the second conductivity type; a second buried layer having the first second conductivity type; a second body having the second conductivity type; a second source region and a second drain region each having the first conductivity type and being separated by the second body; and a second gate positioned in between the second source region and the second drain region.

In at least one embodiment, the semiconductor device further includes a second buried layer tap connected to the second buried layer.

In at least one embodiment, the second buried layer tap has the first conductivity type.

In at least one embodiment, the well comprises a first well, the semiconductor device further comprising: a second well formed in the substrate and having the second conductivity type; and a third well formed between the second well and the first buried layer and having the first conductivity type.

In at least one embodiment, the semiconductor device further includes: a well formed in the substrate and having the second conductivity type; and a second buried layer between the buried layer and the well, the second buried layer having the first conductivity type.

In at least one embodiment, the semiconductor device further includes a buried layer tap connected to the second buried layer.

In at least one embodiment, the buried layer tap has the first conductivity type.

In at least one embodiment, the semiconductor device includes a first vertical thyristor formed by the buried layer, the second buried layer, the body and the source region; and a second vertical thyristor formed by the buried layer, the second buried layer, the body and the drain region.

In at least one embodiment, switching between on and off of the MOS transistor 20 is controlled by voltage applied to the gate, and switching between on and off of the lateral BJT is controlled by voltage applied to the gate and to the second buried layer.

In at least one embodiment, the semiconductor device further includes a body contact configured to be tied to or isolated from the body.

In at least one embodiment, whether the body contact is tied to or isolated from the body is modulated by voltage applied to the buried layer.

In at least one embodiment, the semiconductor device further includes an insulating layer between the body contact and the source region.

In at least one embodiment, the insulating layer does not contact the buried layer.

In at least one embodiment, the semiconductor device further includes second insulating layers that insulate the body from adjacent semiconductor devices.

In at least one embodiment, the second insulating layers extend beneath a surface of the buried layer.

In at least one embodiment, the second insulating layers do not contact the buried layer.

In at least one embodiment, the second insulating layers extend beneath a lower surface of the buried layer.

In at least one embodiment, the gate is connected to the buried layer tap.

In at least one embodiment, the body comprises a fin structure extending perpendicularly from the substrate.

In at least one embodiment, the source region and the drain region are included in the fin structure.

In at least one embodiment, the gate extends down to align with a junction between the body and the buried layer.

In at least one embodiment, the fin structure is tapered to increase capacitive coupling efficiency between the gate and the body.

In at least one embodiment, the buried layer comprises a buried oxide layer.

In another aspect of the present invention, a semiconductor device configured to function as a semiconductor memory device or a transistor with increased on-state drain current, includes: a substrate having a first conductivity type selected from p-type conductivity type and n-type conductivity type; a buried insulating layer;

a body having the first conductivity type; a source region and a drain region each having the second conductivity type and being separated by the body; a charge injector region separated from the source region and the drain region; and a gate positioned in between the source region and the drain region; wherein the semiconductor device is configured to function as a memory device having at least two stable states, or as a transistor with increased on-state drain current, but with no change in off-state drain current, depending on biases that are applied to the semiconductor device.

In at least one embodiment, wherein whether the semiconductor device functions as the memory device having at least two stable states, or as the transistor with increased on-state drain current, but with no change in off-state drain current is governed by an amount of voltage applied to the charge injector region.

In at least one embodiment, a relatively low voltage applied to the charge injector region governs the semiconductor device to function as a MOSFET (metal-oxide-semiconductor field effect transistor) and wherein a relatively high voltage applied to the buried layer governs the semiconductor device to function as the memory device having at least two stable states.

In at least one embodiment, a relatively intermediate high voltage applied to the charge injector region higher than the relatively low voltage and lower than the relatively high voltage, but sufficient to turn on a bipolar junction transistor (BJT) formed by the charge injector region, the body and the source region, turns on a lateral BJT formed by the source region, the body and the drain region, resulting in increased on-state drain current.

In at least one embodiment, the body is ultrathin, comprising a thickness in the range of from 2 nm to 10 nm.

In at least one embodiment, the body is thin, comprising a thickness in the range of from 10 nm to 200 nm.

In at least one embodiment, a first length of the gate between the source region and the drain region is greater than a second length of the gate between the source region and the charge injector region.

In at least one embodiment, the charge injector region comprises a first charge injection region, the semiconductor device further comprising a second charge injector region.

In at least one embodiment, the gate extends between the source region and the drain region, but not between the source region and the first injector region and not between the drain region and the second injector region.

In at least one embodiment, at least one of the source region, drain region and charge injector regions has a first junction depth less than a second junction depth of at least one other of the source region, drain region and charge injector regions.

In at least one embodiment, the source region has the first junction depth and the drain region and at least one of the charge injector regions has the second junction depth.

In at least one embodiment, the semiconductor device further includes a second gate.

In at least one embodiment, the semiconductor device further includes a charge trap layer adjacent at least one of the source region and the drain region.

In at least one embodiment, the charge trap layer directly contacts at least one of the source region and the drain region.

In at least one embodiment, the charge trap layer indirectly contacts at least one of the source region and the drain region via a thin interfacial oxide layer.

In at least one embodiment, the semiconductor device further includes a metal silicide junction located at at least one of: between the source region and the body, and between the drain region and the body.

In at least one embodiment, the semiconductor device further includes an energy band offset region located at at least one of: between the source region and the body, and between the drain region and the body.

In at least one embodiment, the energy band offset region comprises a valence band offset material.

In at least one embodiment, the semiconductor device further includes a recombination center located at at least one of: between the source region and the body, and between the drain region and the body.

In at least one embodiment, the recombination center is formed by doping with deep level impurities.

In at least one embodiment, the deep level impurities comprise at least one of gold or platinum.

In at least one embodiment, the recombination center is formed by introducing crystallinity damage through ion implantation.

In at least one embodiment, ions used for the ion implantation are selected from at least one of the group consisting of: Si ions, Ge ions and Ar ions.

In at least one embodiment, the semiconductor device further includes a control gate positioned above the gate.

In at least one embodiment, the semiconductor device further includes a select gate spaced apart from the gate.

In at least one embodiment, the select gate is positioned in between the drain region and the gate, and an insulating gap region is formed between the select gate and the gate.

In at least one embodiment, a cross-sectional area of the source region is greater than a cross-sectional area of the drain region.

In at least one embodiment, the semiconductor device further includes a control gate spaced apart from the gate.

In at least one embodiment, the control gate is positioned in between the drain region and the gate, and an insulating gap region is formed between the control gate and the gate.

In at least one embodiment, the control gate overlaps the insulating gap region and at least partially overlaps the gate.

In at least one embodiment, a cross-sectional area of the source region is greater than a cross-sectional area of the drain region.

In at least one embodiment, the semiconductor device further includes a resistive change element connected to one of the source region or the drain region.

According to another aspect of the present invention, a method of selectively operating a semiconductor device as a semiconductor memory device or a transistor with increased on-state drain current, includes: providing the semiconductor device comprising a substrate having a first conductivity type selected from p-type conductivity type and n-type conductivity type; a buried layer having a second conductivity type selected from the p-type conductivity type and the n-type conductivity type and being different from the first conductivity type; a body having the first conductivity type; a source region and a drain region each having the second conductivity type and being separated by the body; and a gate positioned in between the source region and the drain region; and selectively operating the semiconductor device as the semiconductor memory device or the transistor, wherein the selectively operating comprises: applying a relatively low voltage to the buried layer to operate the semiconductor device as an ordinary transistor; applying a relatively high voltage to the buried layer to operate the semiconductor device as the semiconductor memory device, wherein the semiconductor memory device has at least two stable states; and applying an intermediate high voltage higher than the relatively low voltage but lower than the relatively high voltage to the buried layer to operate the semiconductor device as the transistor with increased on-state drain current.

In at least one embodiment, the relatively high voltage is sufficiently high to turn on a vertical bipolar junction transistor (BJT) formed by the buried layer, the body and one of the source region or the drain region.

In at least one embodiment, the intermediate high voltage summed with a voltage applied to the gate is sufficiently high to turn on a vertical bipolar junction transistor (BJT) formed by the buried layer, the body and one of the source region or the drain region.

In at least one embodiment, the turn on of the vertical BJT acts as a base current for a lateral BJT formed by the source region, the body and the drain region, turning on the lateral BJT and resulting in increased on-state drain current.

In at least one embodiment, the on-state drain current comprises a sum of current through a MOS transistor formed by the source region, the gate, the drain region and the body; and current through the lateral BJT.

In at least one embodiment, an off-state current, when the intermediate high voltage is applied, is the same as when zero voltage is applied to the buried layer.

In at least one embodiment, the method further includes applying zero voltage to the gate and applying the intermediate high voltage to the drain region, resulting in turning off a MOS transistor formed by the source region, the gate, the drain region and the body; and turning on a lateral bipolar junction transistor (BJT) formed by the source region, the body and the drain region.

In at least one embodiment, switching between on and off of the MOS transistor is controlled by voltage applied to the gate.

In at least one embodiment, the method further includes modulating voltage applied to the buried layer to adjust and trim a skew of the transistor.

In at least one embodiment, the method further includes modulating voltage applied to the buried layer to compensate for change in temperature of the semiconductor device in order to comply with shifts in gate and drain voltages required to turn on the lateral BJT.

In at least one embodiment, the semiconductor device further comprises a body contact that can be selectively connected to or isolated from the body; wherein connection to or isolation of the body contact to or from the body is modulated by an amount of voltage applied to the buried layer.

In at least one embodiment, application of a voltage greater than or equal to a separating threshold voltage to the buried layer forms a depletion region sufficient to isolate the body contact from the body.

In at least one embodiment, application of a voltage greater than or equal to a separating threshold voltage to the buried layer extends a boundary of the depletion region beyond a bottom of an insulating layer separating the body contact from the body.

In at least one embodiment, the method further includes providing a recombination region in the semiconductor device to reduce transient time between on and off states of the semiconductor device.

In another aspect of the present invention, a complementary metal-oxide-semiconductor (MOS) device includes: a substrate having a first conductivity type selected from p-type conductivity type and n-type conductivity type; a first buried layer having a second conductivity type selected from the p-type conductivity type and the n-type conductivity type and being different from the first conductivity type; a first body having the first conductivity type; a first source region and a first drain region each having the second conductivity type and being separated by the first body; a first gate positioned in between the first source region and the first drain region; a well formed in the substrate and having the second conductivity type; a second buried layer having the first second conductivity type; a second body having the second conductivity type; a second source region and a second drain region each having the first conductivity type and being separated by the second body; and a second gate positioned in between the second source region and the second drain region.

In at least one embodiment, the complementary metal-oxide-semiconductor (MOS) device is configured to function as a memory device having at least two stable states, or as a transistor with increased on-state drain current, but with no change in off-state drain current, depending on biases that are applied to the semiconductor device.

In at least one embodiment, the complementary metal-oxide-semiconductor (MOS) device further includes: a first a buried layer tap connected to the first buried layer; and a second buried layer tap connect to the second buried layer.

In at least one embodiment, the first buried layer tap has the second conductivity type and the second buried layer tap has the first conductivity type.

In at least one embodiment, the well comprises a first well, the complementary metal-oxide-semiconductor (MOS) device further including: a second well formed in the substrate and having the second conductivity type; and a third well formed between the second well and the first buried layer and having the first conductivity type.

In another aspect of the present invention, a metal-oxide-semiconductor (MOS) device includes: a substrate having a first conductivity type selected from p-type conductivity type and n-type conductivity type; a buried layer having a second conductivity type selected from the p-type conductivity type and the n-type conductivity type and being different from the first conductivity type; a body having the first conductivity type; a source region and a drain region each having the second conductivity type and being separated by the body; a gate positioned in between the source region and the drain region; a well formed in the substrate and having the second conductivity type; and a second buried layer between the buried layer and the well, the second buried layer having the first conductivity type.

In at least one embodiment, the metal-oxide-semiconductor (MOS) device is configured to function as a memory device having at least two stable states, or as a transistor with increased on-state drain current, but with no change in off-state drain current, depending on biases that are applied to the semiconductor device.

In at least one embodiment, the metal-oxide-semiconductor (MOS) device further includes a buried layer tap connected to the second buried layer.

In at least one embodiment, the buried layer tap has the first conductivity type.

In at least one embodiment, the metal-oxide-semiconductor (MOS) device includes a first vertical thyristor formed by the buried layer, the second buried layer, the body and the source region; and a second vertical thyristor formed by the buried layer, the second buried layer, the body and the drain region.

In another aspect of the present invention, a metal-oxide-semiconductor (MOS) device includes: a substrate having a first conductivity type selected from p-type conductivity type and n-type conductivity type; a buried layer having a second conductivity type selected from the p-type conductivity type and the n-type conductivity type and being different from the first conductivity type; a body having the first conductivity type; a source region and a drain region each having the second conductivity type and being separated by the body; a gate positioned in between the source region and the drain region; a body contact connected to the body; and an insulating layer positioned between the body contact and a portion of the body.

In at least one embodiment, the metal-oxide-semiconductor (MOS) device is configured to selectively connect the body contact to the body or isolate the body contact from the body.

In at least one embodiment, the metal-oxide-semiconductor (MOS) device is configured to function as a memory device having at least two stable states, or as a transistor with increased on-state drain current, but with no change in off-state drain current, depending on biases that are applied to the semiconductor device.

In another aspect of the present invention, a metal-oxide-semiconductor (MOS) device includes: a substrate having a first conductivity type selected from p-type conductivity type and n-type conductivity type; a buried oxide layer;

a body having the first conductivity type; a source region, a drain region and a charge injector region each having the second conductivity type and being separated by the body; and a gate positioned in between the source region and the drain region.

In at least one embodiment, the metal-oxide-semiconductor (MOS) device is configured to function as a memory device having at least two stable states, or as a transistor with increased on-state drain current, but with no change in off-state drain current, depending on biases that are applied to the semiconductor device.

In at least one embodiment, the gate is further positioned in between the source region and the charge injector region and between the drain region and the charge injector region.

In at least one embodiment, the body is ultrathin, comprising a thickness in the range of from 2 nm to 10 nm.

In at least one embodiment, the body is thin, comprising a thickness in the range of from 10 nm to 200 nm.

In another aspect of the present invention, a complementary metal-oxide-semiconductor (MOS) device includes: a substrate having a first conductivity type selected from p-type conductivity type and n-type conductivity type; a buried layer; a first body having the first conductivity type; a first source region and a first drain region each having the second conductivity type and being separated by the first body; a first gate positioned in between the first source region and the first drain region; a second body having the second conductivity type; a second source region and a second drain region each having the first conductivity type and being separated by the second body; a second gate positioned in between the second source region and the second drain region; and an insulating layer separating a first portion of the buried layer underlying the first body from a second portion of the buried layer underlying the second body.

In at least one embodiment, the complementary metal-oxide-semiconductor (MOS) device is configured to function as a memory device having at least two stable states, or as a transistor with increased on-state drain current, but with no change in off-state drain current, depending on biases that are applied to the semiconductor device.

In another aspect of the present invention, a complementary metal-oxide-semiconductor (MOS) device includes: a substrate having a first conductivity type selected from p-type conductivity type and n-type conductivity type; a buried layer; a body having the first conductivity type; a source region and a drain region each having the second conductivity type and being separated by the body; a gate positioned in between the source region and the drain region; and a charge trap layer adjacent at least one of the source region and the drain region.

In at least one embodiment, the charge trap layer directly contacts at least one of the source region and the drain region.

In at least one embodiment, the charge trap layer indirectly contacts at least one of the source region and the drain region via a thin interfacial oxide layer.

In another aspect of the present invention, a complementary metal-oxide-semiconductor (MOS) device includes: a substrate having a first conductivity type selected from p-type conductivity type and n-type conductivity type; a buried layer; a body having the first conductivity type; a source region and a drain region each having the second conductivity type and being separated by the body; a gate positioned in between the source region and the drain region; and a metal silicide junction located at at least one of: between the source region and the body, and between the drain region and the body.

In another aspect of the present invention, a complementary metal-oxide-semiconductor (MOS) device includes: a substrate having a first conductivity type selected from p-type conductivity type and n-type conductivity type; a buried layer; a body having the first conductivity type; a source region and a drain region each having the second conductivity type and being separated by the body; a gate positioned in between the source region and the drain region; and an energy band offset region located at at least one of: between the source region and the body, and between the drain region and the body.

In at least one embodiment, the energy band offset region comprises a valence band offset material.

In another aspect of the present invention, a complementary metal-oxide-semiconductor (MOS) device includes: a substrate having a first conductivity type selected from p-type conductivity type and n-type conductivity type; a buried layer; a body having the first conductivity type; a source region and a drain region each having the second conductivity type and being separated by the body; a gate positioned in between the source region and the drain region; and a metal silicide junction located at at least one of: between the source region and the body, and between the drain region and the body.

In another aspect of the present invention, a complementary metal-oxide-semiconductor (MOS) device includes: a substrate having a first conductivity type selected from p-type conductivity type and n-type conductivity type; a buried layer; a body having the first conductivity type; a source region and a drain region each having the second conductivity type and being separated by the body; a gate positioned in between the source region and the drain region; and a recombination center located at at least one of: between the source region and the body, and between the drain region and the body.

In at least one embodiment, the recombination center is formed by doping with deep level impurities.

In at least one embodiment, the recombination center is formed by introducing crystallinity damage through ion implantation.

In another aspect of the present invention, an inverter gate includes transistors configured to provide increased on-state current, the inverter gate including: a substrate having a first conductivity type selected from p-type conductivity type and n-type conductivity type; a first buried layer having a second conductivity type selected from the p-type conductivity type and the n-type conductivity type and being different from the first conductivity type; a first body having the first conductivity type; a first source region and a first drain region each having the second conductivity type and being separated by the first body; a first gate positioned in between the first source region and the first drain region; a first well formed in the substrate and having the second conductivity type; a second well formed in the substrate and having the first conductivity type; a second buried layer having the first second conductivity type; a second body having the second conductivity type; a second source region and a second drain region each having the first conductivity type and being separated by the second body; a second gate positioned in between the second source region and the second drain region; a first buried well tap connected to the first well and having the second conductivity type; and a second buried well tap connected to the second well and having the first conductivity type.

In another aspect of the present invention, a two input NAND gate includes: two p-channel transistors in parallel and two n-channel transistors in series, wherein each p-channel transistor comprises: a substrate having a first conductivity type selected from p-type conductivity type and n-type conductivity type; a first buried layer having a second conductivity type selected from the p-type conductivity type and the n-type conductivity type and being different from the first conductivity type; a first body having the first conductivity type; a first source region and a first drain region each having the second conductivity type and being separated by the first body; a first gate positioned in between the first source region and the first drain region; and a first well formed in the substrate and having the second conductivity type; and wherein each n-channel transistor comprises: a second well formed in the substrate and having the first conductivity type; a second buried layer having the first second conductivity type; a second body having the second conductivity type; a second source region and a second drain region each having the first conductivity type and being separated by the second body; and a second gate positioned in between the second source region and the second drain region; wherein each transistor is configured to function as a transistor with increased on-state drain current, but with no change in off-state drain current.

In at least one embodiment, the n-channel transistors in series are separated by an isolation region and connected through a conductive layer.

In another aspect of the present invention, a two input NOR gate includes: two p-channel transistors in series and two n-channel transistors in parallel; wherein each p-channel transistor comprises: a substrate having a first conductivity type selected from p-type conductivity type and n-type conductivity type; a first buried layer having a second conductivity type selected from the p-type conductivity type and the n-type conductivity type and being different from the first conductivity type; a first body having the first conductivity type; a first source region and a first drain region each having the second conductivity type and being separated by the first body; a first gate positioned in between the first source region and the first drain region; and a first well formed in the substrate and having the second conductivity type; and wherein each n-channel transistor comprises: a second well formed in the substrate and having the first conductivity type; a second buried layer having the first second conductivity type; a second body having the second conductivity type; a second source region and a second drain region each having the first conductivity type and being separated by the second body; and a second gate positioned in between the second source region and the second drain region; wherein each transistor is configured to function as a transistor with increased on-state drain current, but with no change in off-state drain current.

In at least one embodiment, the p-channel transistors in series are separated by an isolation region and connected through a conductive layer.

In another aspect of the present invention, a boosted transistor in combination with a metal-oxide-semiconductor (MOS) transistor is provided, the boosted transistor including: a substrate having a first conductivity type selected from p-type conductivity type and n-type conductivity type; a first buried layer having a second conductivity type selected from the p-type conductivity type and the n-type conductivity type and being different from the first conductivity type; a body having the first conductivity type; a first source region and a first drain region each having the second conductivity type and being separated by the first body; a first gate positioned in between the first source region and the first drain region; and wherein metal-oxide-semiconductor (MOS) transistor includes: the substrate; the buried layer; a well having the second conductivity type; a second source region and a second drain region each having the first conductivity type and being separated by the well; and a second gate positioned in between the second source region and the second drain region.

In at least one embodiment, bias applied to the buried layer of the boosted transistor is also applied to the well of the metal-oxide-semiconductor (MOS) transistor.

In another aspect of the present invention, a semiconductor device configured to function as a semiconductor memory device or a transistor with increased on-state drain current includes: a substrate having a first conductivity type selected from p-type conductivity type and n-type conductivity type; a buried layer having a second conductivity type selected from the p-type conductivity type and the n-type conductivity type and being different from the first conductivity type; a body having the first conductivity type; a source region and a drain region each having the second conductivity type and being separated by the body; a gate positioned in between the source region and the drain region; and a select gate spaced apart from the gate.

In at least one embodiment, the select gate is positioned in between the drain region and the gate, and an insulating gap region is formed between the select gate and the gate.

In at least one embodiment, the gate is floating and stores non-volatile data in the absence of power.

In at least one embodiment, applying a voltage to the buried layer region enhances current flow to the gate.

In another aspect of the present invention, a semiconductor device configured to function as a semiconductor memory device or a transistor with increased on-state drain current includes: a substrate having a first conductivity type selected from p-type conductivity type and n-type conductivity type; a buried layer having a second conductivity type selected from the p-type conductivity type and the n-type conductivity type and being different from the first conductivity type; a body having the first conductivity type; a source region and a drain region each having the second conductivity type and being separated by the body; a gate positioned in between the source region and the drain region; and a control gate spaced apart from the gate.

In at least one embodiment, the control gate is positioned in between the drain region and the gate, and an insulating gap region is formed between the control gate and the gate.

In at least one embodiment, the control gate overlaps the insulating gap region and at least partially overlaps the gate.

In at least one embodiment, the gate is floating and stores non-volatile data in the absence of power.

In at least one embodiment, applying a voltage to the buried layer region enhances current flow to the gate.

These and other advantages and features of the invention will become apparent to those persons skilled in the art upon reading the details of the devices and methods as more fully described below.

BRIEF DESCRIPTION OF THE DRAWINGS

In the course of the detailed description to follow, reference will be made to the attached drawings. These drawings show different aspects of the present invention and, where appropriate, reference numerals illustrating like structures, components, materials and/or elements in different figures are labeled similarly. It is understood that various combinations of the structures, components, materials and/or elements, other than those specifically shown, are contemplated and are within the scope of the present invention.

FIG. 1 is a schematic, cross-sectional illustration of a conventional MOS device.

FIG. 2 is a schematic, cross-sectional illustration of a MOS device according to the present invention.

FIG. 3 is a schematic, cross-sectional illustration of a MOS device according to another embodiment of the present invention.

FIG. 4 is a schematic, cross-sectional illustration of a MOS device with buried layer tap region according to an embodiment of the present invention.

FIG. 5 illustrates an equivalent circuit representing a MOS device according to an embodiment of the present invention.

FIG. 6 illustrates an equivalent capacitor circuit model representing a MOS device according to an embodiment of the present invention.

FIG. 7 illustrates drain current versus gate voltage characteristics for various voltages applied to a buried layer, representing a MOS device according to an embodiment of the present invention.

FIG. 8 illustrates minimum gate and drain voltage to activate an intrinsic lateral BJT for different voltages applied to a buried layer, representing a MOS device according to an embodiment of the present invention.

FIG. 9 is a schematic, cross-sectional illustration of a CMOS device implemented in standard dual well process according to an embodiment of the present invention.

FIG. 10 is a schematic, cross-sectional illustration of a CMOS device implemented in standard triple well process according to another embodiment of the present invention.

FIG. 11 is a schematic, cross-sectional illustration of a MOS device according to another embodiment of the present invention.

FIG. 12 illustrates an equivalent circuit of the MOS device shown in FIG. 11.

FIG. 13 illustrates an equivalent capacitor circuit model representing the MOS device shown in FIG. 11.

FIG. 14 is a schematic, cross-sectional illustration of a MOS device with body tap and buried layer tap region according to an embodiment of the present invention.

FIGS. 15A-15B are schematic, cross-sectional illustrations of a MOS device with body tap and buried layer tap region with the depletion region boundary according to an embodiment of the present invention.

FIG. 16 is a schematic, cross-sectional illustration of a MOS device with body tap and buried layer tap region having dual STI depth according to an embodiment of the present invention.

FIGS. 17A-17B are schematic, cross-sectional illustrations of a MOS device with body tap and buried layer tap region having dual STI depth with the depletion region boundary according to an embodiment of the present invention.

FIGS. 18A-18B are schematic, cross-sectional illustrations of a MOS device with body tap and buried layer tap region having another dual STI depth with the depletion region boundary according to an embodiment of the present invention.

FIGS. 19A-19B are schematic, cross-sectional illustrations of a MOS device with body tap and buried layer tap region tied to gate having another dual STI depth with the depletion region boundary according to an embodiment of the present invention.

FIG. 20A is a schematic, top view of a MOS device comprising a fin structure according to an embodiment of the present invention.

FIG. 20B is a schematic, cross-sectional view of the MOS device of FIG. 20A taken along line I-I′.

FIG. 20C is a schematic, cross-sectional view of the MOS device of FIG. 20A taken along line II-II′.

FIG. 20D is a schematic, three-dimensional view of the MOS device of FIG. 20A.

FIG. 21A is a schematic, illustration of a fin type MOS device according to another embodiment of the present invention.

FIG. 21B is a schematic, illustration of a fin type MOS device according to another embodiment of the present invention.

FIG. 21C is a schematic, illustration of a complementary fin type MOS device according to another embodiment of the present invention.

FIG. 22 is a schematic, cross-sectional illustration of a fin type MOS device with buried layer tap region according to an embodiment of the present invention.

FIG. 23 is a schematic, top view of a MOS device comprising a fin structure having a body tap according to an embodiment of the present invention.

FIG. 24 is a schematic, cross-sectional view of the MOS device of FIG. 23 taken along line I-I′.

FIG. 25 is a schematic, cross-sectional view of the MOS device of FIG. 23 taken along line II-II′.

FIG. 26A is a schematic, top-view illustration of a MOS device having a buried insulator layer according to an embodiment of the present invention.

FIG. 26B is a schematic, cross-sectional view of the MOS device of FIG. 26A taken along line A-B.

FIG. 26C is a schematic, cross-sectional view of the MOS device of FIG. 26A taken along line C-D.

FIG. 27 illustrates an equivalent circuit representing the MOS device shown in FIG. 26.

FIG. 28 is a schematic, cross-sectional illustration of a CMOS device according to another embodiment of the present invention.

FIG. 29 is a schematic, top-view illustration of a MOS device having a buried insulator layer according to another embodiment of the present invention.

FIG. 30 is a schematic, top-view illustration of a MOS device having a buried insulator layer according to another embodiment of the present invention.

FIGS. 31A-31B are schematic, top-view illustrations of a MOS device having a buried insulator layer according to another embodiment of the present invention.

FIG. 31C is a schematic, cross-sectional illustration of a MOS device having a buried insulator layer according to another embodiment of the present invention.

FIG. 32A is a schematic, cross-sectional illustration of a MOS device with charge trap layer lined in the trench isolation region according to an embodiment of the present invention.

FIG. 32B is a schematic, cross-sectional illustration of a MOS device with metal silicided junction partially contacting the body region according to an embodiment of the present invention.

FIG. 32C is a schematic, cross-sectional illustration of a MOS device with junction with energy band offset compared to body region according to an embodiment of the present invention.

FIG. 32D is a schematic, cross-sectional illustration of a MOS device with recombination centers disposed near the junction according to an embodiment of the present invention.

FIG. 33A is a schematic, cross-sectional illustration of a memory cell according to an embodiment of the present invention.

FIG. 33B is a schematic, cross-sectional illustration of a memory cell according to another embodiment of the present invention.

FIG. 33C is a schematic, cross-sectional illustration of a memory cell according to another embodiment of the present invention.

FIGS. 34A-34B schematically illustrate an equivalent circuit representation of the memory cells shown in FIGS. 33A-33C.

FIG. 35 schematically illustrates equivalent capacitor circuit representation of the memory cells shown in FIGS. 33A-33C.

FIG. 36 schematically illustrates multiple cells of the type from any of FIGS. 33A-33C joined in an array according to an embodiment of the present invention.

FIGS. 37A-37B illustrate bias conditions applied on the terminals of a memory cell of FIG. 36 to perform a write logic-0 operation.

FIG. 38 illustrates drain current versus control gate voltage characteristics for various voltages applied to a buried layer, representing a memory cell according to an embodiment of the present invention.

FIG. 39 illustrates minimum gate and drain voltage to activate a lateral BJT for different voltages applied to a buried layer, representing a memory cell according to an embodiment of the present invention.

FIGS. 40A-40B illustrate bias conditions applied on the terminals of a memory cell of FIG. 36 to perform a write logic-1 operation.

FIGS. 41A-41B illustrate bias conditions applied on the terminals of a memory cell of FIG. 36 to perform a read operation.

FIG. 42 illustrates drain current versus control gate characteristics during a read operation performed to a memory cell according to an embodiment of the present invention.

FIG. 43 is a schematic, cross-sectional illustration of a memory cell according to another embodiment of the present invention.

FIG. 44 illustrates bias conditions applied on the terminals of the memory cell shown in FIG. 43 to perform a write logic-0 operation.

FIG. 45 illustrates bias conditions applied on the terminals of the memory cell shown in FIG. 43 to perform a write logic-1 operation.

FIG. 46 illustrates bias conditions applied on the terminals of a memory cell shown in FIG. 43 to perform a read operation.

FIG. 47 is a schematic, cross-sectional illustration of a memory cell according to another embodiment of the present invention.

FIG. 48 illustrates bias conditions applied on the terminals of the memory cell shown in FIG. 47 to perform a write logic-0 operation.

FIG. 49 illustrates bias conditions applied on the terminals of the memory cell shown in FIG. 47 to perform a write logic-1 operation.

FIG. 50 illustrates bias conditions applied on the terminals of the memory cell shown in FIG. 47 to perform a read operation.

FIG. 51 is a schematic, cross-sectional illustration of a non-volatile memory cell comprising a resistive change element according to another embodiment of the present invention.

FIG. 52 illustrates an inverter constructed using a MOS device having increased on-state current according to an embodiment of the present invention.

FIG. 53 illustrates a two-input NAND gate constructed using a MOS device having increased on-state current according to an embodiment of the present invention.

FIG. 54 illustrates a two-input NAND gate constructed using a MOS device having increased on-state current according to another embodiment of the present invention.

FIG. 55 illustrates a two-input NOR gate constructed using a MOS device having increased on-state current according to an embodiment of the present invention.

FIG. 56 illustrates a MOS device having increased on-state current and a conventional MOS device, where the well of the conventional MOS device is electrically connected to the buried well layer of the MOS device having increased on-state current, according to an embodiment of the present invention.

FIG. 57 illustrates an equivalent circuit representing a MOS device according to another embodiment of the present invention.

FIG. 58 illustrates a MOS device having a body tap current according to another embodiment of the present invention.

FIG. 59 illustrates a flip flop constructed using a semiconductor device according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Before the present MOSFETS, memory cells and arrays are described, it is to be understood that this invention is not limited to particular embodiments described, as such may, of course, vary. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to be limiting, since the scope of the present invention will be limited only by the appended claims.

Where a range of values is provided, it is understood that each intervening value, to the tenth of the unit of the lower limit unless the context clearly dictates otherwise, between the upper and lower limits of that range is also specifically disclosed. Each smaller range between any stated value or intervening value in a stated range and any other stated or intervening value in that stated range is encompassed within the invention. The upper and lower limits of these smaller ranges may independently be included or excluded in the range, and each range where either, neither or both limits are included in the smaller ranges is also encompassed within the invention, subject to any specifically excluded limit in the stated range. Where the stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included in the invention.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Although any methods and materials similar or equivalent to those described herein can be used in the practice or testing of the present invention, the preferred methods and materials are now described. All publications mentioned herein are incorporated herein by reference to disclose and describe the methods and/or materials in connection with which the publications are cited.

It must be noted that as used herein and in the appended claims, the singular forms “a”, “an”, and “the” include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to “a cell” includes a plurality of such cells and reference to “the region” includes reference to one or more regions and equivalents thereof known to those skilled in the art, and so forth.

The publications discussed herein are provided solely for their disclosure prior to the filing date of the present application. The dates of publication provided may be different from the actual publication dates which may need to be independently confirmed.

FIG. 1 illustrates a prior art complimentary metal-oxide semiconductor (CMOS) 1 in which n-channel and p-channel MOSFETs are fabricated on the same chip having a substrate 12. A BJT is inherently formed during manufacture of the MOSFET. The intrinsic BJT is connected in parallel to the MOSFET, where emitter, base, and collector of the intrinsic BJT are formed from the source 16, channel 24, and drain 18 of the MOSFET 1, respectively. The MOSFET 1 further includes a gate 60, gate insulator 62 and insulators 26. The intrinsic BJT of MOSFET 1 rarely contributes to the drain current. Currently, the manufacturing process and operation scheme for conventional MOSFETs are designed to nullify the effect of the inherent BJT.

Referring to FIG. 2, a semiconductor device 50 according to an embodiment of the present invention is shown. Semiconductor device 50 may function as a semiconductor memory device or a transistor with increased on-state drain current, but with no change in the off-state drain current, depending on the bias applied to the semiconductor device 50.

Semiconductor device 50 includes a substrate 12 of a first conductivity type such as p-type, for example. Substrate 12 is typically made of silicon, but may also comprise, for example, germanium, silicon germanium, gallium arsenide, and/or other semiconductor materials. In some embodiments of the invention, substrate 12 can be the bulk material of the semiconductor wafer. In another embodiment shown in FIG. 3, substrate 12A of a first conductivity type (for example, p-type) can be a well of the first conductivity type embedded in a well 29 of the second conductivity type, such as n-type. The well 29 in turn can be another well inside substrate 12B of the first conductivity type (for example, p-type). In another embodiment, well 12A can be embedded inside the bulk of the semiconductor wafer of the second conductivity type (for example, n-type). These arrangements allow for segmentation of the substrate terminal, which is connected to 12A. To simplify the description, the substrate 12 will usually be drawn as the semiconductor bulk material as it is in FIG. 2.

Semiconductor device 50 also includes a buried layer 22 of a second conductivity type, such as n-type, for example; a body 24 of the first conductivity type, such as p-type, for example; and source/drain regions 16 and 18 of the second conductivity type, such as n-type, for example. Buried layer 22 may be formed by an ion implantation process on the material of substrate 12. Alternatively, buried layer 22 can be grown epitaxially on top of substrate 12 or formed through a solid state diffusion process.

The body 24 of the first conductivity type is bounded on top by source 16, drain 18, and insulating layer 62 (or by surface 14 in general), on the sides by insulating layers 26, and on the bottom by buried layer 22. Body 24 may be the portion of the original substrate 12 above buried layer 22 if buried layer 22 is implanted. Alternatively, body 24 may be epitaxially grown on top of the buried layer 22 through a solid state diffusion process.

A source 16 and drain 18 having a second conductivity type, such as n-type, for example, are provided in body 24, so as to bound a portion of the top of the body 24 in a manner discussed above, and is exposed at surface 14. Source 16 and drain 18 may be formed by an implantation process on the material making up substrate 12, according to any implantation process known and typically used in the art. Alternatively, a solid state diffusion or a selective epitaxial growth process could be used to form source 16 and drain 18.

A gate 60 is positioned in between the source 16 and the drain 18, above body 24. The gate 60 is insulated from the body 24 by an insulating layer 62. Insulating layer 62 may be made of silicon oxide and/or other dielectric materials, including high-K dielectric materials, such as, but not limited to, tantalum peroxide, titanium oxide, zirconium oxide, hafnium oxide, and/or aluminum oxide. The gate 60 may be made of, for example, polysilicon material or metal gate electrode, such as tungsten, tantalum, titanium and their nitrides.

Insulating layers 26 (like, for example, shallow trench isolation (STI)), may be made of silicon oxide, for example, though other insulating materials may be used. Insulating layers 26 insulate semiconductor device 50 from adjacent semiconductor devices 50. The bottom of insulating layer 26 may reside inside the buried layer 22 allowing buried layer 22 to be continuous as shown in FIGS. 2 and 3. Alternatively, the bottom of insulating layer 26 may reside below the buried layer 22 (not shown). This requires a shallower insulating layer 26B (where the bottom of insulating layer 26B resides inside the buried layer 22), which insulates the body 24, but allows the buried layer 22 to be continuous in the perpendicular direction of the cross-sectional view shown in FIG. 2 and FIG. 3. For simplicity, only semiconductor device 50 with continuous buried layer 22 in all directions will be shown from hereon.

FIG. 4 illustrates a cross-sectional illustration of a semiconductor device 50 shown in FIG. 2 with buried layer 22 connected to buried layer tap 36 according to an embodiment of the present invention. The buried layer tap 36 having a second conductivity type, such as n-type, for example, is connected to the buried layer 22 through the buried tap body 44 having a second conductivity type, such as n-type. The buried tap body 44 may be formed by an implantation process following the same process step of the well formation of complementary type of MOS transistor such as p-channel device. The buried tap 36 may be formed by an implantation process or selective epitaxial growth process following the same process step of the source and drain formation of complementary type of MOS transistor such as p-channel device. For example, if buried tap body 44 and buried tap 36 are formed by an ion implantation process, the implant energy (which determines the depth of the implant) for buried tap body 44 is higher than the implant energy for buried layer tap 36.

The operation of the semiconductor device 50 will be described using an n-channel device as an example. The operation of a p-channel device follows the same principle, but the polarity of the applied voltages will be opposite that of the n-channel device (using the source voltage as the reference).

FIG. 5 illustrates an equivalent circuit representation of semiconductor device 50. Inherent in semiconductor device 50 are metal-oxide-semiconductor (MOS) transistor 20, formed by source 16, gate 60, drain 18, and body 24, and vertical BJTs 30 a and 30 b, formed by buried layer 22, body 24, and source 16 or drain 18, respectively. Also inherent in semiconductor device 50 is lateral BJT 30 c, formed by source 16, body 24, and drain 18.

FIG. 6 schematically illustrates an equivalent capacitor circuit representation of semiconductor device 50 shown in FIGS. 2-5. The body 24 potential (V_(B)) is capacitively coupled with gate oxide capacitance, source side junction capacitance, drain side junction capacitance, and buried layer junction capacitance. Therefore, the body 24 potential (V_(B)) can be perturbed by the gate 60 voltage, source 16 voltage, drain 18 voltage, and buried layer 22 voltage (V_(BNL) for buried n-layer and V_(BPL) for buried p-layer voltage).

Semiconductor device 50 may function as a memory device having at least two stable states and as a transistor with increased on-state drain current, but with no change in the off-state drain current, depending on the applied bias to the semiconductor memory device 50. In one embodiment, the properties of the semiconductor device 50 are governed by the voltage applied to the buried layer 22.

FIG. 7 schematically illustrates drain 18 current versus gate 60 voltage characteristics for various buried layer 22 voltage. In this plot, it is important to note that the applied drain 18 voltage is assumed to be a voltage that does not exceed that which would cause an impact ionization process near the junction between the body 24 and the drain 18. If the voltage applied to the drain region 18 is sufficiently high to cause impact an ionization process near the junction between the body 24 and the drain 18, an increase in the current flow (from the drain region 18 to the source region 16) may also be observed, as described for example in “Hysteresis I-V Effects in Short-Channel Silicon MOSFETs”, Boudou, A. and Doyle, B. S., IEEE Electron Device Letters, vol. EDL-8, no. 7, July 1987, or the kink effect observed in the silicon-on-insulator (SOI) wafer as described for example in “Single-Transistor Latch in SOI MOSFETs”, Chen, C.-E. D., et al, IEEE Electron Device Letters, vol. 9, no. 12, December 1988, which are hereby incorporated herein, in their entireties, by reference thereto. Because the voltage applied to the drain region 18 to cause impact ionization process is typically higher than the operating voltage of the transistor, this may result in degradation of the transistor performance and reliability over time.

If the buried layer 22 is biased at low voltage such as zero volts, the drain 18 current versus the gate 60 voltage characteristic 100 a shows ordinary MOSFET characteristics.

At high voltage V_(BNL2) applied to the buried layer 22, the semiconductor device 50 will function as a memory device having at least two stable states. If the constant voltage applied to the buried layer 22 is sufficiently high that if body 24 potential is greater than the potential required to turn-on vertical BJT 30 a, regardless of the gate 60 and the drain 18 voltages, electron hole pairs are generated near a junction between the body 24 and the buried layer 22 even at the gate voltage of zero. The resulting hot electrons flow into the buried layer 22 while the resulting hot holes will subsequently flow into the body region 24. When the following condition is met: β×(M−1)≈1—where β is the forward common-emitter current gain of the bipolar transistors 30 a or 30 b and M is the impact ionization coefficient—the amount of holes injected into the body region 24 compensates for the charge lost due to p-n junction forward bias current between the body region 24 and the source line region 16 or bit line region 18 and due to holes recombination. This process maintains the charge (i.e. holes) stored in the body region 24 which will keep the n-p-n bipolar transistors 30 a and 30 b on for as long as a positive bias is applied to the buried well region 22. The state where the body potential is sufficiently high and is maintained by the hole current generated at the junction of body 24 and buried layer 22 is referred to as the logic-1 state of the memory device 50. As shown in the drain 18 current versus gate 60 voltage characteristics for high buried layer 22 voltage 100 c of FIG. 7, the lateral BJT 30 c current flows even at the zero gate voltage, when the memory device 50 is in logic-1 state.

If body 24 is neutrally charged (the voltage on body 24 being equal to the voltage on grounded drain region 18), a state corresponding to logic-0, no (or low) current will flow through the n-p-n bipolar devices 30 a and 30 b. The bipolar devices 30 a and 30 b will remain off and no impact ionization occurs. Consequently memory cells in the logic-0 state will remain in the logic-0 state.

Several operations can be performed to semiconductor device 50 operating as a memory device such as holding, read, write logic-1 and write logic-0 operations, and have been described for example in U.S. Patent Application Publication No. 2010/00246284 to Widjaja et al., titled “Semiconductor Memory Having Floating Body Transistor and Method of Operating” (“Widjaja-1”) and U.S. Patent Application Publication No. 2010/0034041, “Method of Operating Semiconductor Memory Device with Floating Body Transistor Using Silicon Controlled Rectifier Principle” (“Widjaja-2”), which are both hereby incorporated herein, in their entireties, by reference thereto.

If the buried layer 22 is biased at a positive voltage (but less positive than the positive voltage which results in the drain 18 current versus gate 60 voltage characteristics 100 c), gate 60 and drain 18 voltages can elevate body 24 potential to be greater than a potential required to turn-on vertical BJT 30 a by capacitive coupling. When the vertical BJT 30 a is turned on, electrons from source 18 (emitter) flow to the buried layer 22 (collector) of the vertical BJT 30 a. The constant voltage applied to the buried layer 22 is enough to cause impact ionization process, and electron hole pairs are generated near a junction between the body 24 and the buried layer 22. The generated electrons are collected by the positively biased buried layer 22, while the generated holes flow into the body 24. These generated holes act as a base current of the lateral BJT 30 c, which turns on the lateral BJT 30 c. As a result, the on-state drain current becomes the sum of MOS transistor 20 current and lateral BJT 30 c current. As shown in the drain 18 current versus gate 60 voltage characteristics for high buried layer 22 voltage 100 b of FIG. 7, the on-state drain current is boosted compared to the on-state drain current with the buried layer 22 biased at zero. If desired, the on-state drain current can be further boosted by increasing the voltage applied to the buried layer 22. However, the off-state drain current can be the same as the off-state drain current with the buried layer 22 biased at zero, because the body 24 potential at the gate voltage of zero becomes smaller than the threshold voltage for turning on the vertical BJT 30 c. Therefore, at a positive bias V_(BNL1) (less positive than the positive voltage V_(BNL2) which results in a memory device having at least two stable states), semiconductor device 50 functions as a transistor with increased on-state drain current, but with no change in the off-state drain current. Also notice that the drain 18 current versus gate 60 voltage characteristics of 100 c exhibits a steep slope (<60 mV/dec) when at the gate 60 voltage when the lateral BJT 30 c is first activated.

When the constant voltage applied to the buried layer 22 is less than a voltage to cause an impact ionization process near the junction between the buried layer 22 and the body 24, no lateral BJT 30 c action take place at any body 24 potentials. For a constant voltage applied to the buried layer 22 that is greater than or equal to that required to cause an impact ionization process, FIG. 8 represent the drain 18 voltage and gate 60 voltage that start to form body 24 potential to turn on the vertical BJT 30 a. In other words, the lines (102 a, 102 b, and 102 c) indicate the minimum gate 60 and drain 18 voltages to activate the lateral BJT 30 c at a given buried layer 22 voltage. The voltages at upper and right region of the line causes the lateral BJT 30 c to be turned on. A line may locate above power supply voltage Vdd for a low voltage applied to the buried layer 22 (for example, line 102 a). In this case, no lateral BJT 30 c would be activated within the normal operation voltage ranging from 0V to Vdd. For a very high voltage applied to the buried layer 22, a line may locate inside Vdd (for example, line 102 c). In this case, the lateral BJT 30 c is activated even at gate 60 voltage of zero. For some high voltage applied to the buried layer 22, a line (for example, line 102 b) may intersect to the Vdd lines (dotted lines). In this case, the lateral BJT 30 c is activated even at gate 60 voltage of Vdd, but the lateral BJT 30 c can be turned off at gate 60 voltage of zero. Therefore, various operations can be attained according to the desired characteristics.

Several operations can be performed by MOS device 50 having increased on-state drain current, but with no change in the off-state drain current. When a supply voltage (Vdd) such as 1.0 volt is applied to the gate 60 and the drain 18, depending on the voltage applied to the buried layer 22, both MOS transistor 20 and lateral BJT 30 c can be turned on, which results in higher on-state drain current than the conventional MOSFET, or MOS transistor 20 can be turned on while the lateral BJT 30 c is turned off, which results in the same on-state drain current compared to the conventional MOSFET. When zero volts is applied to the gate 60 and Vdd such as 1.0 volt is applied to the drain 18, MOS transistor 20 can be turned off while the lateral BJT 30 c is turned on, which results in a high off-state drain leakage current, or both MOS transistor 20 and lateral BJT 30 c can be turned off, which results in lowest off-state drain current. According to an embodiment of the present invention, aforementioned various operational states can be determined by different levels of voltage applied to the buried layer 22. The switching between on and off of MOS transistor 20 is associated with a voltage applied to gate 60. The switching between on and off of lateral BJT 30 c is associated with a voltage applied to gate 60 and buried layer 22.

In one particular non-limiting embodiment, V_(BNL2) is about +2.0 volts, V_(BNL1) is about +1.5 volts, and low V_(BL) is a positive voltage lower than V_(BNL1). However, these voltage levels may vary, while maintaining the relationship that V_(BNL2) is more positive than V_(BNL1). These voltage levels may depend for example on the doping profile and the depth of the buried layer region 22.

FIG. 9 is a cross-sectional illustration of a complementary MOS device 150 configured with n-channel 150 a and p-channel 150 b devices on the same wafer implemented in a standard dual well process. The n-channel MOS device 150 a is positioned inside p-well 12 while the p-channel MOS device 150 b is positioned inside n-well 112. Source 116, drain 118, buried layer 122, and buried layer tap 136 of the p-channel device 150 b are configured to have opposite conductivity type compared to corresponding components of the n-channel device 150 a and as explained in reference to FIG. 2. Ion implantation process conditions to form a buried p-layer 122 and n-well 112 in the p-channel 150 b device are designed to avoid shorting between buried p-layer 122 and p-well 12. A two-step ion implantation process, where a p-type ion implantation is followed by n-type ion implantation or vice versa, may be necessary in the p-channel 150 b device. Extra n-type ion implantation to form buried n-well 112 is conditioned to compensate the high doping concentration of the tail profile of the buried p-layer 122 to prevent shorting between buried p-layer 122 and p-well 12.

The physical mechanism, operations, and characteristics of the n-channel 150 a and p-channel 150 b device are analogous to the MOS device 50 explained from FIG. 5 through FIG. 8. However, when the source is assumed to be a reference, the operation voltages of n-channel and p-channel device are of opposite polarity from each other.

FIG. 10 is a cross-sectional illustration of a complementary MOS device 250 configured with n-channel 250 a and p-channel 250 b devices on the same wafer implemented in a standard triple well process. The n-channel MOS device 250 a is positioned inside p-well 12A that is inside the deep n-well 29 while the p-channel MOS device 250 b is positioned inside n-well 112. Source 116, drain 118, buried layer 122, and buried layer tap 136 of the p-channel device 250 b are configured to have opposite conductivity type of the n-channel device 250 a and that explained in regard to FIG. 2. Ion implantation process conditions to form a buried n-layer 22 and p-well 12A in the n-channel 250 a device are designed to avoid shorting between buried n-layer 22 and deep n-well 29. Ion implantation process conditions to form a buried p-layer 122 and n-well 112 in the p-channel 250 b device are designed to avoid shorting between buried p-layer 122 and p-well 12A. Two-step ion implantation processes, where n-type ion implantation is followed by p-type ion implantation or vice versa, may be necessary in both n-channel 250 a and p-channel 250 b devices. In n-channel device 250 a, extra p-type ion implantation is conditioned to compensate the high doping concentration of the tail profile of the buried n-layer 22 to prevent shorting between buried n-layer 22 and deep n-well 29. In p-channel device 250 b, extra n-type ion implantation is conditioned to compensate the high doping concentration of the tail profile of the buried p-layer 122 to prevent shorting between buried p-layer 122 and p-substrate 12B.

The physical mechanism, operations, and characteristics of the n-channel 250 a and p-channel 250 b device are analogous to the MOS device 50 explained from FIG. 5 through FIG. 8. However, when the source is assumed to be a reference, the operation voltages of n-channel and p-channel device are of opposite polarity to each other.

Referring to FIG. 11, a MOS device 350 according to another embodiment of the present invention is shown. MOS device 350 includes a substrate 12 of a first conductivity type such as p-type, for example. The MOS device 350 includes a deep well 29 of the second conductivity type, such as n-type. MOS device 350 also includes a first buried layer 32 of a first conductivity type, such as p-type, for example; a second buried layer 22 of a second conductivity type, such as n-type, for example; a body 24 of the first conductivity type, such as p-type, for example; and source/drain 16 and 18 of the second conductivity type, such as n-type, for example. Buried layers 22 and 32 may be formed by an ion implantation process on the material of substrate 12. Alternatively, buried layer 22 and 32 can be grown epitaxially on top of substrate 12 or formed through a solid state diffusion process.

The body 24 of the first conductivity type and the second buried layer 22 of the second conductivity type are bounded on top by source 16, drain 18, and insulating layer 62 (or by surface 14 in general), on the sides by insulating layers 26, and on the bottom by the first buried layer 32 of the first conductivity type. While the body 24 and the second buried layer 22 are not directly connected to any terminals, the first buried layer 32 is connected to the buried layer tap 46 according to the present invention. The buried layer tap 46 having a first conductivity type, such as p-type, for example, is connected to the first buried layer 32.

FIG. 12 illustrates an equivalent circuit representation of MOS device 350. Inherent in MOS device 350 are metal-oxide-semiconductor (MOS) transistor 20, formed by source 16, gate 60, drain 18, and body 24, and vertical pnpn thyristors 330 a and 330 b, formed by first buried layer 32, second buried layer 22, body 24, and source 16 or drain 18, respectively. Also inherent in MOS device 350 is lateral BJT 30, formed by source 16, body 24, and drain 18.

FIG. 13 schematically illustrates an equivalent capacitor circuit representation of MOS device 350 shown in FIG. 11. The body 24 potential (V_(B)) is capacitively coupled with gate 60 oxide capacitance, source 16 side junction capacitance, drain 18 side junction capacitance, first buried layer 32 junction capacitance, and second buried layer 22 junction capacitance. Therefore, the body 24 potential (V_(B)) can be perturbed by the gate 60 voltage, source 16 voltage, drain 18 voltage, and first buried layer 32 voltage.

Several operations can be performed by MOS device 350. When a supply voltage (Vdd) such as 1.0 volt is applied to the gate 60 and the drain 18, both MOS transistor 20 and lateral BJT 30 can be turned on, which results in higher on-state drain current than the conventional MOSFET, or MOS transistor 20 can be turned on while the lateral BJT 30 are turned off, which results in the same on-state drain current compared to the conventional MOSFET. When zero volts are applied to the gate 60 and Vdd such as 1.0 volt is applied to the drain 18, MOS transistor 20 can be turned off while the lateral BJT 30 is turned on, which results in a high off-state drain leakage current, or both MOS transistor 20 and lateral BJT 30 c can be turned off, which results in lowest off-state drain current. According to an embodiment of the present invention, aforementioned various operational states can be determined by different levels of voltages applied to the first buried layer 32. The switching between on and off of MOS transistor 20 is associated with a voltage applied to gate 60. The switching between on and off of lateral BJT 30 is associated with a voltage applied to gate 60 and first buried layer 32.

Drain 18 current versus gate 60 voltage characteristics of MOS device 350 for various first buried layer 32 voltages may also be illustrated by the drain current versus gate voltage relationship shown in FIG. 7 and the drain voltage versus gate voltage relationship shown in FIG. 8. If the first buried layer 32 is biased at low voltage such as zero volts, the drain 18 current versus the gate 60 voltage characteristic 100 a shows ordinary MOSFET characteristics.

If the constant voltage applied to the first buried layer 32 is very high for body 24 potential to be greater than the potential required to turn-on vertical thyristor 330 a, regardless of the gate 60 and the drain 18 voltages, the electron hole pairs are generated near a junction between the body 24 and the second buried layer 22 even at the gate voltage of zero. As a result, the lateral BJT 30 current flows even at the zero gate voltage due to the hole supply.

If the first buried layer 32 is biased at a positive voltage (but less positive than the positive voltage which results in the drain 18 current versus gate 60 voltage characteristics 100 c), gate 60 and drain 18 voltages can elevate body 24 potential to be greater than a potential required to turn-on thyristor 330 a by capacitive coupling. When the vertical thyristor 330 a is turned on, electrons from source 18 (emitter) flow toward the second buried layer 22 of the vertical thyristor 330 a. If the electrical potential induced the second buried layer 22 is enough to cause an impact ionization process, the electron hole pairs are generated near a junction between the body 24 and the second buried layer 22. The generated holes flows into the body 24. These generated holes act as a base current of the lateral BJT 30, which turns on the lateral BJT 30. As a result, the on-state drain current becomes a sum of MOS 20 current and lateral BJT 30 current. Therefore, the on-state drain current is boosted compared to the on-state drain current with the buried layer 22 biased at zero. If desired, the on-state drain current could be further boosted by increasing the voltage applied to the first buried layer 32. However, the off-state drain current remains the same as the off-state drain current with the first buried layer 32 biased at zero, because the body 24 potential at the gate voltage of zero becomes smaller than the threshold voltage for turning on the vertical thyristor 330 a. Also notice that the drain 18 current versus gate 60 characteristics 100 c exhibits a steep slope (<60 mV/dec) when at the gate 60 voltage when the lateral BJT 30 is first activated.

In one embodiment of the present invention, a fixed low or zero voltage applied to the first buried layer 32 is selected to turn off the lateral BJT 30 c at any gate 60 and drain 18 voltages. In this case, the MOS device 350 may be used as a regular transistor.

In another embodiment of the present invention, a fixed high voltage applied to the first buried layer 32 is selected to turn on the lateral BJT 30 c at the gate voltage of zero. In this case, the MOS device 350 may be used as a single-transistor-latch or single-transistor memory.

In another embodiment of the present invention, the fixed voltage applied to the first buried layer 32 is selected to turn on the lateral BJT 30 c at the gate voltage of Vdd but turn off the lateral BJT 30 c at the gate voltage of zero. In this case, the MOS device 350 results in boosted on-state drain current but the off-state drain current remains the same as the off-state drain current of a regular transistor.

In another embodiment of the present invention, the high voltage applied to the first buried layer 32 is modulated to adjust and trim a skew of the transistor.

In another embodiment of the present invention, the voltage applied to the first buried layer 32 is modulated according to the change of device temperature in order to comply with the shift of gate 60 and drain 18 voltages to turn on the lateral BJT 30 c.

FIGS. 14-16 illustrate MOS device 450 according to another embodiment of the present invention. MOS device 450 comprises a body contact 136 that can be tied or isolated to body 24 of the MOS device 450. The isolation or connection of body contact 136 to the body 24 is modulated by the back bias voltage applied to the buried layer 22. It should be understood that the FIGS. 14-16 can be complementary types based on either dual well or triple well process as explained in FIG. 9 and FIG. 10. Furthermore, the MOS device 450 can be extended to the thyristor type as explained in the FIG. 11-13.

Referring to FIG. 14, the body 24 of the MOS device 450 is connected to the body contact 136 with an insulating layer 26 in between. One difference between the MOS device 450 and the MOS device 50 is that the buried layer 22 is formed not to contact the bottom of the insulating layer 26. Therefore the body 24 of the MOS device 450 is connected to the body contact 136. More specifically, the body 24 and the body contact 136 can be ‘electrically’ tied (FIG. 15A) or separated (FIG. 15B) by the depletion region boundary 5 in the body 24 side formed between the body 24 and the buried layer 22. FIGS. 15A-15B show the MOS device 450 shown in FIG. 14 with depletion region boundary 5 in the body 24 side formed between the body 24 and the buried layer 22. However the other depletion region boundaries formed in between the body 24 and the source 16, and the body 24 and the drain 18, are not shown in FIGS. 15A-15B. Also, the depletion region boundary 5 in the buried layer 22 side formed between the body 24 and the substrate 12 is not shown.

When about zero volts is applied to the buried layer 22, the depletion region boundary 5 does not isolate the body 24 from the body contact 136, as shown in FIG. 15A. As reverse voltage applied to the buried layer 22 (a positive voltage for n-type buried layer 22 or a negative voltage for p-type buried layer 22) increases, the depletion region boundary 5 moves upward and approaches to the bottom of the insulating layers 26. When the depletion region boundary reaches the bottoms of the insulating layer as well as when it extends above the bottoms, the body 24 is separated into the body 24A in transistor region and the body 24B in the body tapping region by the insulating layer 26 and the depletion region boundary 5 as illustrated in FIG. 15B. The minimum reverse voltage applied to the buried layer 22 that separates (isolates) the body contact 136 from the body 24 is referred to as the separating threshold voltage. As reverse voltage applied to the buried layer 22 further exceeds the separating threshold voltage, the body 24A is kept isolated from the body contact 136, as shown in FIG. 15B.

The body contact 136 may be grounded throughout the operation. When the MOS device 450 is to be turned off, zero or a voltage less than separating threshold voltage is applied to the buried layer 22, and as a result the body 24 is connected to the body contact 136. As a result, the excess of majority carriers in the body 24 can be swept out toward to the body contact 136. When the MOS device 450 is turned on, a voltage greater than separating threshold voltage is applied to the buried layer 22, so that the body 24 is isolated from the body contact 136 in a manner as described above. As a result, on-state drain current is enhanced by the sum of MOS transistor 20 and the lateral BJT 30 c due to the same mechanism explained throughout FIG. 2 to FIG. 8.

As the bottom of the insulating layer 26 does not reside inside the buried layer 22 in FIG. 14 and FIGS. 15A-15B, the voltages applied to the body contact 136 and the buried layer 22 can be shared with the neighboring MOS devices 450.

FIGS. 16 and 17A-17B illustrate MOS device 550 according to another embodiment of the present invention, which comprises body contact 136 with an insulating layer 126 in between body contact 136 and source 16. MOS device 550 allows for sharing of the buried layer 22 voltage, but the potential of the body 24 remains isolated. Insulating layers 126 are disposed between the transistor region 16/24/18 and the body tapping region 136, as well as between the buried layer tapping region 36 and the transistor region 16/24/18, while additional insulating layers 26 are the same as ordinary isolating layers such as shallow trench isolation that are used to isolate adjacent devices. The depth of the insulating layer 126 is shallower than the insulating layer 26, which may be fabricated by the dual STI process. The bottom of insulating layer 26 resides inside the buried layer 22 allowing buried layer 22 to be continuous as shown in FIGS. 16 and 17A-17B. However, the bottom of the insulating layer 126 is formed not to contact the buried layer 22, so the body 24 of the MOS device 550 is connected to the body contact 136, but the voltage applied to the body contact 136 does not affect neighboring MOS devices 550. The device turn-on and turn-off operation follows the same mechanism as MOS device 450 illustrated in FIGS. 14 and 15.

FIGS. 18A-18B illustrate MOS device 650 according to another embodiment of the present invention, where both buried layer 22 voltage and body 24 voltage are not shared between adjacent MOS devices 650. Source 16 and body 24 are connected to the body contact 136 with an insulating layer 126 in between. Insulating layers 126 are disposed between the transistor region and the body tapping region 136 or the buried layer tapping region 36, while additional insulating layers 26 are the same as ordinary isolating layers such as shallow trench isolation that is used to isolate adjacent devices. A depth of the insulating layer 126 is shallower than the insulating layer 26, which may be fabricated by the dual STI process. The bottom of insulating layer 26 resides below the buried layer 22 allowing buried layer 22 to be isolated within the device unit as illustrated in FIGS. 18A-18B. The bottom of the insulating layer 126 is formed not to contact the buried layer 22 so the body 24 of the MOS device 650 is connected to the body contact 136. Therefore, the voltages applied to the body contact 136 and the buried layer 22 through the buried layer tap 36 and the buried tap body 44 does not affect neighboring MOS devices 650. The device turn-on and turn-off operation follows the same mechanism as MOS device 450 illustrated in FIGS. 14 and 15A-15B.

In MOS devices 50, 150, 250, 350, 450, 550, and 650, the voltages applied to the gate 60 and the buried layer 22 are independently controlled. FIGS. 19A-19B illustrate another embodiment of the present invention where the gate 60 and the buried layer 22 are tied. Referring to FIGS. 19A-19B, the gate 60 and the buried layer tap 36 of the MOS device 650 shown in FIG. 18A-18B are connected. This connection may be accomplished by a metallization process. The buried layer 22 is therefore biased by the same voltage as that applied to the gate 60. When the gate 60 is biased zero to turn off the MOS device 650, the depletion region boundary 5 is not sufficiently formed to allow for the body 24 connected to body contact 136 to be isolated therefrom as shown in FIG. 19A, because the voltage applied to the buried layer 22 that is the same as that applied to gate 60 is less than the separating threshold voltage. As a result, the excess of majority carrier in the body 24 can be swept out to the body contact 136 as quickly as the gate voltage ramp down. The buried layer 22 and the insulating layer 126 may be configured for the depletion region boundary 5 to be formed to isolate the body region 24 at the buried layer 22 voltage of the drive voltage of the device. In such case, when the gate 60 is biased by drive voltage to turn on the MOS device 650, the depletion region boundary 5 is formed to separate the body 24 from the body contact 136 as shown in FIG. 19B. As a result, on-state drain current is boosted by a sum of MOS transistor 20 and the lateral BJT 30 c due to the same mechanism explained throughout FIG. 2 to FIG. 8.

FIGS. 20A-20C illustrate a top view and cross-sectional views of MOS device 50F comprising a fin structure 52 according to another embodiment of the present invention. Fin structure 52 extends perpendicularly from the substrate 12 to form a three-dimensional structure and comprises body 24 having a first conductivity type with buried layer region 22 having a second conductivity type and located below the body 24. Substrate 12 is typically made of silicon, but may also comprise, for example, germanium, silicon germanium, gallium arsenide, and/or other semiconductor materials. In some embodiments of the invention, substrate 12 can be the bulk material of the semiconductor wafer.

The operation of MOS device 50F follows the same principle as MOS device 50 explained throughout FIGS. 2-8, where increased on-state current can be obtained through intrinsic bipolar junction transistor (BJT).

FIG. 20D illustrates a schematic three-dimensional view of MOS device 50F. Fin type MOS device 50F also includes a buried layer 22 of a second conductivity type, such as n-type, for example; a fin type body 24 of the first conductivity type, such as p-type, for example; and source/drain regions 16 and 18 of the second conductivity type, such as n-type, for example. Buried layer 22 may be formed by an ion implantation process on the material of substrate 12. Alternatively, buried layer 22 can be grown epitaxially on top of substrate 12 or formed through a solid state diffusion process.

The fin type body 24 of the first conductivity type is bounded on top by source 16, drain 18, and insulating layer 62, on the sides by insulating layer 26, and on the bottom by buried layer 22. Fin type body 24 may be the portion of the original substrate 12 above buried layer 22 if buried layer 22 is implanted. Alternatively, fin type body 24 may be epitaxially grown on top of the buried layer 22 through a solid state diffusion process.

A source 16 and drain 18 having a second conductivity type, such as n-type, for example, are provided in body 24, so as to bound a portion of the top of the fin type body 24 in a manner discussed above. Source 16 and drain 18 may be formed by an implantation process on the material making up substrate 12, according to any implantation process known and typically used in the art. Alternatively, a solid state diffusion or a selective epitaxial growth process could be used to form source 16 and drain 18.

A gate 60 is positioned in between the source 16 and the drain 18, above body 24. The gate 60 is insulated from the fin type body 24 by an insulating layer 62. Insulating layer 62 may be made of silicon oxide and/or other dielectric materials, including high-K dielectric materials, such as, but not limited to, tantalum peroxide, titanium oxide, zirconium oxide, hafnium oxide, and/or aluminum oxide. The gate 60 may be made of, for example, polysilicon material or metal gate electrode, such as tungsten, tantalum, titanium and their nitrides.

Insulating layers 26 (like, for example, shallow trench isolation (STI)), may be made of silicon oxide, for example, though other insulating materials may be used. Insulating layers 26 insulate MOS device 50F from adjacent fin type MOS devices 50F. The bottom of insulating layer 26 may reside inside the buried layer 22 allowing buried layer 22 to be continuous as shown in FIGS. 20A-20D and 21A-21C. Alternatively, the bottom of insulating layer 26 may reside below the buried layer 22 (not shown). This requires a shallower insulating layer 26, which insulates the body 24, but allows the buried layer 22 to be continuous in direction of the I-I′ cross-sectional view shown in FIG. 20B. For simplicity, only MOS device 50F with continuous buried layer 22 in all directions will be shown from hereon.

FIG. 22 is across-sectional illustration of a fin type MOS device 50F shown in FIGS. 20A-20D and 21A with buried layer 22 connected to buried layer tap 36 according to an embodiment of the present invention. The buried layer tap 36 having a second conductivity type, such as n-type, for example, is connected to the buried layer 22 through the buried tap body 44 having a second conductivity type, such as n-type. The buried tap body 44 may be formed by an implantation process following the same process step of the well formation of complementary fin type of MOS transistor such as p-channel device. The buried tap 36 may be formed by an implantation process or selective epitaxial growth process following the same process step of the source and drain formation of complementary type of MOS transistor such as p-channel device.

FIG. 21A illustrates a fin type MOS device according to another embodiment of the present invention. In this embodiment, the bottom of the gate 60 is extended down to align to the junction between the body 24 and the buried layer 22. This increases the capacitive coupling efficiency between the gate 60 voltage and the body 24 potential.

FIG. 21B illustrates a fin type MOS device according to another embodiment of the present invention. In order to increase the capacitive coupling efficiency between the gate 60 voltage and the fin type body 24 potential, the fin type body 24 is tapered. The gate 60 voltage controllability to the junction potential between the fin type body 24 and the buried layer 22 may be increased due to the wider fin width near the junction and the angle between the gate 60 and the junction angle 23 between the fin type body 24 and the buried layer 22 becomes less than 90°.

FIG. 21C illustrates a complementary fin type MOS device 150F comprising n-channel 150 a and p-channel 150 b devices on the same wafer implemented in a standard dual well process. The n-channel MOS device 150 a is positioned inside p-type substrate 12 while the p-channel MOS device 150 b is positioned inside n-well 112. Source 116, drain 118, buried layer 122, and buried layer tap (not shown) of the p-channel device 150 b are configured to have opposite conductivity type of the n-channel device explained in FIGS. 20A-20C and 21B. Ion implantation process conditions to form a buried p-layer 122 and n-well 112 in the p-channel 150 b device are designed to avoid shorting between buried p-layer 122 and p-well 12. A two-step ion implantation process, where a p-type ion implantation is followed by n-type ion implantation or vice versa, may be performed in the p-channel 150 b device. Extra n-type ion implantation to form buried n-well 112 may be conditioned to compensate the high doping concentration of the tail profile of the buried p-layer 122 to prevent shorting between buried p-layer 122 and p-well 12. Furthermore, in order to prevent shorting between buried p-layer 122 and p-well 12, a dual-depth STI process may be introduced. The STI region 126 deeper than the insulating layer 26 may physically isolate the buried p-layer 122 and the p-well 12.

The effects and results of the n-channel 150 a and p-channel 150 b device are analogous to the MOS device 50 explained from FIG. 5 through FIG. 8. However, when the source is assumed to be a reference, the operation voltages of n-channel and p-channel device are opposite each other.

FIGS. 23-25 illustrate a top view and cross-sectional views of MOS device 450F comprising a fin structure 52 according to another embodiment of the present invention. The operation of MOS device 450F follows the same principle as MOS device 450 illustrated in FIGS. 14-16, where the body 24 connection to the body contact region 136 can be modulated by the back bias voltage applied to the buried layer region 22. Increased on-state current is also obtained through intrinsic bipolar junction transistor (BJT).

FIGS. 26A-26C illustrate a schematic top view and cross section views of a MOS device 50S comprising a buried oxide (BOX) layer 28 according to another embodiment of the present invention. MOS device 50S may be fabricated on silicon-on-insulator (SOI), germanium-on-insulator (GOI), silicon-germanium-on-insulator (SiGeOI), strained silicon-on-insulator (sSOI), strained germanium-on-insulator (sGOI), or strained silicon-germanium-on-insulator (sSiGeOI) substrate. The MOS device 50S includes a substrate 12, a buried oxide layer 28, a body 24 of a first conductivity type, such as p-type conductivity for example, bounded on top by surface 14 and insulating layer 62, on the sides by source 16, drain 18, and charge injector 22 of a second conductivity type, and at the bottom by buried oxide layer 28. Source 16, drain 18, and charge injector 22 may be formed by an implantation process, according to any implantation process known and typically used in the art. Alternatively, a solid state diffusion or a selective epitaxial growth process could be used to form source 16, drain 18, and charge injector 22.

A gate 60 is positioned in between the source 16, the drain 18, and the charge injector 22 above the body 24. The gate 60 is insulated from the body 24 by an insulating layer 62. Insulating layer 62 may be made of silicon oxide and/or other dielectric materials, including high-K dielectric materials, such as, but not limited to, tantalum peroxide, titanium oxide, zirconium oxide, hafnium oxide, and/or aluminum oxide. The gate 60 may be made of, for example, polysilicon material or metal gate electrode, such as tungsten, tantalum, titanium and their nitrides.

Insulating layers 26 (like, for example, shallow trench isolation (STI)), may be made of silicon oxide, for example, though other insulating materials may be used. Insulating layers 26 isolate body 24 of the MOS device 50S from body 24 of adjacent MOS devices 50S.

The thickness of the body 24 may be ultrathin, such as from 2 nm to 10 nm, to provide a fully depleted channel device. Alternatively, the thickness of the body 24 may be moderately thin, such as from 10 nm to 200 nm, to provide a partially depleted channel device.

FIG. 27 illustrates an equivalent circuit representation of MOS device 50S. Inherent in MOS device 50S are metal-oxide-semiconductor (MOS) transistor 20, formed by source 16, gate 60, drain 18, and body 24, and BJTs 30 a and 30 b, formed by charge injector 22, body 24, and source 16 or drain 18, respectively. The BJT formed by charge injector 22, body 24, and source 16 is herein specially referred as the current boosting device 30 a. Also inherent in MOS device 50S is parallel BJT 30 c, formed by source 16, body 24, and drain 18. During the operation of a MOS device 50S, the current boosting device 30 a is used to amplify a drain 18 current of MOS device 50S.

The operation of the MOS device 50S follows the same principle as MOS device 50, where increased on-state current can be obtained through intrinsic bipolar junction transistor (BJT) 30 c parallel to the MOS transistor 20 through an application of reverse bias voltage (for example, a positive voltage for n-type MOS device 50S) to the charge injector region 22.

FIG. 28 is a cross-sectional illustration of a complementary MOS device 150S configured with n-channel 150 a and p-channel 150 b devices on the same SOI wafer. Body 124, source 116, drain 118, and charge injector 122 of the p-channel device 150 b are configured to have opposite conductivity type of corresponding features of the n-channel device 150 a. The effects and results of the n-channel 150 a and p-channel 150 b devices are analogous to the MOS device 50S illustrated in FIG. 27. However, when the source is assumed to be a reference, the polarity of operation voltages of n-channel and p-channel device are opposite each other.

FIG. 29 illustrates a schematic top view of a MOS device 250S according to another embodiment of the present invention. The voltage applied to the charge injector 22 may be desired to be identical to Vdd applied to the drain 18. In this case, if the gate length across source to-drain 60 a is the same as the gate length across source-to-charge injector 60 b, the electric fields near the drain junction and the charge injector junction can both cause impact ionization. In order to prevent impact ionization near the drain junction, the gate length across source-to-drain 60 a may be designed to be larger than the gate length across source-to-charge injector 60 b.

FIG. 30 illustrates a MOS device 350S according to another embodiment of the present invention. The MOS device 350S comprises two charge injector regions 22.

FIG. 31A illustrates a MOS device 450S according to another embodiment of the present invention. The MOS device 450S comprises charge injector regions 22 apart from the source 16 and the drain 18 but no gate is placed in between the source 16 and the charge injector 22, and no gate is placed between the drain 18 and the charge injector 22, while gate 60 is placed between the source 16 and drain 18. In order to form the charge injector 22, an additional masking step may be needed. An exemplary process step to form charge injector 22 is shown in FIG. 31B. After the gate 60 formation step, a lithography step is performed to form a blocking layer 15, such as photoresist for example. An ion implantation of a second conductivity (e.g. n-type implant) is used to form the source 16, drain 18, and charge injector 22, allowing the charge injector 22 to be spaced apart from the source 16 and the drain 18. The blocking layer 15 is then subsequently removed.

FIG. 31C illustrates a MOS device 550S according to another embodiment of the present invention. The regions of second conductivity type in MOS device 550S may have different junction depths. In FIG. 31C, the source 16 is shown to be shallower than the drain 18 and the charge injector 22 to allow for the body 24 to be continuous across the MOS device 550S. Furthermore, the MOS device may or may not comprise another optional gate stack 64, 66. Furthermore, when the optional gate stack 64, 66 is present, the optional gate may or may not be left electrically floating.

The transient time for the transistor having increased on-state drain current, but with no change in the off-state drain current (for example, transistor 50, 150, 250, 350, 450, 550, 650, 50F, 150F, 450F, 50S, 150S, 250S, 350S, 450S, 550S) from the on-state (with increased drain current) to the off-state (with low off-state drain current) may be improved by limiting excess majority carrier lifetime. During on-state, the MOS device 50 requires that the body 24 has a large lifetime for body region excess majority carriers to boost the drive current. When the electrons are injected from the source 16 (emitter) to the body 24 (base), most of these electrons are swept in to the buried layer 22 (collector) with some recombining with the base region majority carriers. A small amount of recombination may occur, but a continuous supply of body 24 region majority-carriers is sustained to boost the on-state drive current. Therefore, the transient time for the transistor 50 from the on-state to the off-state may be improved by providing a recombination region made by several means that will be described below. However, if the population of these majority carriers is too limited, the operation of vertical BJT 30 a is inhibited and subsequently no current boosting will occur. All of the described methods will only alter the majority carrier lifetime while the conductivity type and channel mobility may remain substantially unchanged.

FIG. 32A is a schematic, cross-sectional illustration of a MOS device 50 with charge trap layer 27 such as silicon nitride lined in the trench isolation region 26 according to an embodiment of the present invention. The charge trap layer 27 is either directly contacted to the sidewall of the body 24 region or indirectly contacted through the very thin interfacial oxide in between (not shown). The charge trap layer 27 such as silicon nitride contains substantial number of charge trap centers that may absorb the excess majority carrier.

FIG. 32B is a schematic, cross-sectional illustration of a MOS device 50 with metal silicided junction partially contacting to body 24 region according to an embodiment of the present invention. The metal silicide regions 16A and 18A may contact the body 24 region near the sides of the source 16 and drain 18 region, respectively. Alternatively, the metal silicide 16A is formed only on the source side 16 (not shown). The Schottky junction formed by metal silicide region 16A and the body 24 may facilitate the majority carrier recombination.

FIG. 32C is a schematic, cross-sectional illustration of a MOS device 50 with junction with energy band offset compared to body region according to an embodiment of the present invention. The energy band offset regions 16B and 18B may contact the body 24 region near the bottoms of the source 16 and drain 18 regions. Alternatively, the energy band offset region 16B may be formed only the source 16 side (not shown). For an n-type channel MOS, the valence band offset material is embedded in the source 16 and the drain 18 for the excess majority carrier (holes) to be preferentially evacuated through the source 16. For a p-type channel MOS, the conduction band offset material is embedded in the source 16 and the drain 18 for the excess majority carrier (electrons) to be preferentially evacuated through the source 16.

FIG. 32D is a schematic, cross-sectional illustration of a MOS device 50 with recombination centers 17 disposed near the junction between source 16 and body 24 and, optionally, between drain 18 and body 24 according to an embodiment of the present invention. One general approach is by doping with deep level impurities, such as gold or platinum. Another general approach is to introduce crystallinity damage through ion implantation through such as Si, Ge, or Ar implantation. Another general approach is by using radiation damage to produce defects in the silicon crystal lattice structure.

The charge recombination regions explained in FIG. 32A to FIG. 32D can be symmetrically formed at both the source 16 and the drain 18 for process convenience. However, these charge recombination regions may also be formed only at the source side region in order to inhibit drive current degradation and junction leakage occurring near the drain side.

FIG. 52 illustrates an inverter gate 200A constructed from transistors 50 having increased on-state current. Inverter gate 200A includes n-channel transistor SON and p-channel transistor 50P. The n-channel transistor SON comprises a p-type body 24 (n-channel transistor SON is located within p-well in FIG. 11), while the p-channel transistor 50P comprises an n-type body 124 (p-channel transistor 50P is located within n-well in FIG. 10). FIG. 52 also shows that the n-channel transistor SON is located within buried n-well layer and the p-channel transistor 50P is located within buried p-well layer. FIG. 52 also illustrates the buried n-well layer of n-channel transistor SON is then connected through buried n-well tap 36, while the buried p-well layer of p-channel transistor 50P is connected through buried p-well tap 136. It is important to note that the conductivity of the buried layer tap is the same as the conductivity of the transistor 50 having increased on-state current. In a conventional CMOS circuit, the tap layer and the transistor have different conductivity type. For example, a conventional n-channel transistor is paired with a p-type tap, and a conventional p-channel transistor is paired with an n-type tap.

The n-channel transistor SON is located within a buried n-well layer and the p-channel transistor 50P is located within a buried p-well layer. In another embodiment, the buried n-well layer can be embedded inside another well region (see for example FIG. 3).

Another example of how transistors 50 having boosted on-state current may be used to construct logic gates is shown in FIG. 53, where an example of a two-input NAND gate 200B constructed from boosted transistors 50 is shown. A two-input NAND gate is constructed from two p-channel transistors 50P in parallel, with two n-channel transistors 50N in series. As shown in FIG. 53, the two boosted n-channel transistors 50N in series are separated by an isolation region 26 and connected through a conductive layer (for example, a metal layer shown as wire 25 in FIG. 53). In a conventional CMOS circuit, the two n-channel transistors share a common diffusion region and not separated by an isolation region. Similar to the inverter gate example shown in FIG. 52, the n-channel transistors 50N are paired with an n-type tap 36, and the p-channel transistors 50P are paired with a p-type tap 136.

FIG. 54 illustrates another exemplary embodiment of a two-input NAND gate 200C comprising two p-channel transistors 50P in parallel and two n-channel transistors 50N in series. The two n-channel transistors in series are separated by an isolation region 26 and connected through a conductive layer (for example, a metal layer shown as wire 25 in FIG. 54) and is positioned side-by-side to reduce the height of the two-input NAND gate. Similarly, the n-channel transistors 50N are paired with an n-type tap 36, and the p-channel transistors 50P are paired with a p-type tap 136.

Another exemplary embodiment of a logic gate constructed using transistors 50 having boosted on-state current is shown in FIG. 55, where an example of a two-input NOR gate 200D constructed from boosted transistors 50 is shown. A two-input NOR gate 200D is constructed from two n-channel transistors 50N in parallel, and two p-channel transistors 50P in series. As shown in FIG. 55, the two p-channel transistors 50P in series are separated by an isolation region 26 and connected through a conductive layer (for example, a metal layer shown as wire 25 in FIG. 55). The n-channel transistors 50N are paired with an n-type tap 36, and the p-channel transistors 50P are paired with a p-type tap 136.

FIG. 56 illustrates two transistors, a transistor 50 having a boosted on-state current, and a MOS transistor 40. Transistor 50 comprises body 24 having a first conductivity type, source and drain regions (16 and 18) having a second conductivity type, and a buried layer 30 having a second conductivity type. As has been described, with buried layer 30 being properly biased, transistor 50 can have an increased on-state current, while maintaining the same off-state current.

Transistor 40 is a MOS transistor having different conductivity type as boosted transistor 50. For example, if boosted transistor 50 is an n-channel MOS, then transistor 40 is a p-channel MOS. Transistor 40 comprises well 12′ having a second conductivity type and source and drain regions 20′ and 22′ having first conductivity type. The well 12′ of the transistor 40 and the buried layer 30 have the same conductivity type and therefore are electrically connected. The bias applied to the buried layer 30 of the boosted transistor 50 is then also applied to the well 12′ of the transistor 40.

The example shown in FIG. 56 illustrates how a boosted transistor 50 may be used in conjunction with a MOS transistor 40 to modulate the performance of both transistors simultaneously. Biasing the buried layer 30 to boost the on-current of the transistor 50 will increase the strength of the transistor 50. Simultaneously, biasing the buried layer 30 will result in an increase of the threshold of the transistor 40, effectively reducing the strength of the transistor 40.

Characteristics of logic gates can be dynamically modified by combining transistors 50 with boosted on-current and regular MOS transistors 40, where the well 12′ of the regular MOS transistors 40 is electrically connected to the buried layer of the transistors 50 having boosted on-state current. For example, an inverter can be constructed using transistors 50 and 40 as shown in FIG. 56. The switching point of the inverter can be modulated by biasing the buried layer 30.

FIG. 57 illustrates an equivalent circuit representation of transistor 750, where there are two parallel paths for current flow from drain region to source region: MOS 20 and bipolar transistor 30 c. The base of the bipolar transistor 30 c can be modulated by applying a bias to the body region 24. The conductivity of the MOS 20 is modulated by the bias applied to the gate 60 and body 24, and the conductivity of the bipolar transistor 30 c is modulated by the bias applied to the body 24.

FIG. 58 illustrates an exemplary implementation of transistor 750 according to an embodiment of the present invention. Transistor 750 is similar to transistor 50, but with a body tap 20 having the same conductivity as body 24, where body tap 20 is used to bias the body 24.

Transistor 750 may be used to construct a logic gate, where the gate 60 and body 24 function as the input terminals of the gate. For example, an OR gate can be constructed using transistor 750, where a high conductivity through transistor 750 is obtained when both the input terminals (gate 60 and body 24) are both high. The transistor 750 is still conducting when one of the input terminals is high, as current will flow through either the MOS 30 or the bipolar transistor 30 c. When both input terminals are low, the transistor 750 will not be conducting.

Transistor 750 may also be combined with an inverter to construct other logic gates. For example, although the OR gate described above will be conductive when either input terminal or both input terminals are high, the highest conductivity is obtained when both input terminals are high. Therefore, an inverter with a modulated switching point (for example, using the exemplary combination of boosted transistor 50 and a conventional MOS 40 as shown in FIG. 56) may be used in conjunction with transistor 750, so that the inverter is only switched when the conductivity of the transistor 750 is the highest. This, for example, may be used to construct a NAND gate.

FIG. 59 illustrates an example of semiconductor device 50 used as a flip flop according to an embodiment of the present invention. By applying negative voltage pulses to the gate 60 and drain 18 terminals, the state of the semiconductor device 50 will alternate between low and high states.

Non-volatile memory devices, such as flash erasable programmable read only memory (Flash EPROM) devices, retain stored data even in the absence of power supplied thereto. Unfortunately, non-volatile memory devices typically operate more slowly than volatile memory devices. Furthermore, operation of non-volatile memory devices typically requires a higher voltage (higher voltage than the core logic transistor operating voltage). Therefore an integrated circuit comprising Flash memory devices typically requires high voltage transistors. This introduces challenges especially that the core logic transistor operating voltage is continuously being scaled to lower voltage (for example 1.0V or less), see for example “Embedded Nonvolatile Memories: A Key Enabler for Distributed Intelligence”, K. Baker, pp. 1-4, 2012 4th IEEE International Memory Workshop (IMW), which is hereby incorporated herein, in its entirety, by reference thereto. Therefore, it is desired to have a non-volatile memory cell with reduced operating voltage.

FIG. 33A illustrates a schematic cross-sectional view of a memory cell 1450 according to an embodiment of the present invention.

The cell 1450 includes a substrate 12 of a first conductivity type, such as a p-type conductivity type, for example. Substrate 12 is typically made of silicon, but may comprise germanium, silicon germanium, gallium arsenide, carbon nanotubes, or other semiconductor materials known in the art. The substrate 12 has a surface 14. A first region 16 having a second conductivity type, such as n-type, for example, is provided in substrate 12 and which is exposed at surface 14. A second region 18 having the second conductivity type is also provided in substrate 12, which is exposed at surface 14 and which is spaced apart from the first region 16. First and second regions 16 and 18 are formed by an implantation process formed on the material making up substrate 12, according to any of implantation processes known and typically used in the art. Alternatively, first and second regions 16 and 18 are formed by a selective epitaxial growth process formed on the material making up substrate 12, according to any of epitaxial growth processes known and typically used in the art.

A buried layer 22 of the second conductivity type is also provided in the substrate 12, buried in the substrate 12, as shown. Region 22 is also formed by an ion implantation process on the material of substrate 12. A floating body region 24 of a first conductivity type is bounded by surface 14, first and second regions 16, 18 and insulating layers 26 (e.g. shallow trench isolation (STI)), which may be made of silicon oxide, for example. Insulating layers 26 insulate cell 1450 from neighboring cells 1450 when multiple cells 1450 are joined to make a memory device. The bottom of insulating layer 26 may reside inside the buried region 22 allowing buried region 22 to be continuous as shown in FIG. 33A. Alternatively, the bottom of insulating layer 26 may reside below the buried region 22 as shown in the cross-sectional view of another embodiment of memory cell 1450 in FIG. 33B. This requires a shallower insulating layer 28 (shown in dashed lines in FIG. 33B), which insulates the floating body region 24, but allows the buried layer 22 to be continuous in the perpendicular direction of the cross-sectional view shown in FIG. 33B. For simplicity, only memory cell 1450 with continuous buried region 22 in all directions will be shown from hereon.

A floating gate or trapping layer 60 is positioned in between the regions 16 and 18, and above the surface 14. Trapping layer/floating gate 60 is insulated from surface 14 by an insulating layer 62. Insulating layer 62 may be made of silicon oxide and/or other dielectric materials, including high-K dielectric materials, such as, but not limited to, tantalum peroxide, titanium oxide, zirconium oxide, hafnium oxide, and/or aluminum oxide. Floating gate/trapping layer 60 may be made of polysilicon material. If a trapping layer is chosen, the trapping layer may be made from silicon nitride or silicon nanocrystal, etc. (for example as described in “Flash Memory Cell-An Overview”, Pavan, P. et al., Proceedings of the IEEE 85 no. 8, 1997, pp. 1248-1271, “NROM™—a new technology for non-volatile memory products”, Bloom, I. et. al., Solid-State Electronics, vol. 46, issue 11, November 2002, pp. 1757-1763 and “Scalability of split-gate charge trap memories down to 20 nm for low-power embedded memories”, Masoero, L. et. al., 2011 International Electron Devices Meeting, 9.5, which are all hereby incorporated herein, in their entireties, by reference thereto). Whether a floating gate 60 or a trapping layer 60 is used, the function is the same, in that they hold data in the absence of power. The primary difference between the floating gate 60 and the trapping layer 60 is that the floating gate 60 is a conductor, while the trapping layer 60 is an insulator layer. Thus, typically one or the other of trapping layer 60 and floating gate 60 are employed in device 1450, but not both.

A control gate 66 is positioned above floating gate/trapping layer 60 and insulated therefrom by insulating layer 64 such that floating gate/trapping layer 60 is positioned between insulating layer 62 and surface 14 underlying floating gate/trapping layer 60, and insulating layer 64 and control gate 66 positioned above floating gate/trapping layer 60, as shown. Control gate 66 is capacitively coupled to floating gate/trapping layer 60. Control gate 66 is typically made of polysilicon material or metal gate electrode, such as tungsten, tantalum, titanium and their nitrides. The relationship between the floating gate/trapping layer 60 and control gate 66 is similar to that of a non-volatile stacked gate floating gate/trapping layer memory cell. The floating gate/trapping layer 60 functions to store non-volatile memory data and the control gate 66 is used for memory cell selection.

In some embodiments of the invention, substrate 12 can be the bulk material of the semiconductor wafer. In another embodiment shown in FIG. 33C, substrate 12A of a first conductivity type (for example, p-type) can be a well of the first conductivity type embedded in a well 29 of the second conductivity type, such as n-type. The well 29 in turn can be another well inside substrate 12B of the first conductivity type (for example, p-type). In another embodiment, well 12A can be embedded inside the bulk of the semiconductor wafer of the second conductivity type (for example, n-type). These arrangements allow for segmentation of the substrate terminal, which is connected to 12A. To simplify the description, the substrate 12 will usually be drawn as the semiconductor bulk material as it is in FIG. 33A.

The cell 1450 in FIGS. 33A-33D includes five terminals: word line (WL) terminal 70, source line (SL) terminal 72, bit line (BL) terminal 74, buried layer (BNL for buried n-type layer or BPL for buried p-type layer) terminal 76, and substrate terminal 78. Terminal 70 is connected to control gate 66. Terminal 72 is connected to first region 16 and terminal 74 is connected to second region 18. Alternatively, terminal 72 can be connected to second region 18 and terminal 74 can be connected to first region 16. Terminal 76 is connected to buried layer 22. Substrate terminal 78 is connected to substrate 12 below buried layer 22.

FIG. 34A illustrates an equivalent circuit representation of memory cell 1450. Inherent in cell 1450 is floating gate/trapping layer transistor 20 formed by source line region 16, floating gate or trapping layer 60, control gate 66, drain region 18, and floating body region 24, where the floating gate or trapping layer modulates the threshold voltage of the transistor 20, for example as described in “Flash Memory”, edited by P. Cappelletti, C. Golla, P. Olivo, E. Zanoni, p. 6, which is hereby incorporated herein, in its entirety, by reference thereto. Similarly, bipolar transistors 30 a and 30 b formed by the buried layer 22, floating body region 24, and the source line region 16/drain region 18, respectively, are also inherent in cell 1450. In addition, bipolar transistor 30 c formed by source line region 16, floating body region 24, and drain region 18 is also inherent in cell 1450, as shown in FIG. 34B.

FIG. 35 schematically illustrates an equivalent capacitor circuit representation of cell 1450 shown in FIGS. 33A-34. The body 24 potential (V_(FB)) is capacitively coupled with control gate 66 oxide capacitance, floating gate 60 oxide capacitance, source 16 side junction capacitance, drain 18 side junction capacitance, and buried layer 22 junction capacitance. Therefore, the control gate 66 voltage, source 16 voltage, drain 18 voltage, and buried layer 22 voltage can modulate the floating body 24 potential (V_(FB)).

FIG. 36 schematically illustrates an exemplary embodiment of a memory array 1480 of memory cells 1450 (four exemplary instances of memory cell 1450 being labeled as 1450 a, 1450 b, 1450 c and 1450 d) arranged in rows and columns. In many, but not all, of the figures where array 1480 appears, representative memory cell 1450 a will be representative of a “selected” memory cell 1450 when the operation being described has one (or more in some embodiments) selected memory cells 1450. In such figures, representative memory cell 1450 b will be representative of an unselected memory cell 1450 sharing the same row as selected representative memory cell 1450 a, representative memory cell 1450 c will be representative of an unselected memory cell 1450 sharing the same column as selected representative memory cell 1450 a, and representative memory cell 1450 d will be representative of a memory cell 1450 sharing neither a row or a column with selected representative memory cell 1450 a.

Present in FIG. 36 are word lines 70 a through 70 n, source lines 72 a through 72 n, bit lines 74 a through 74 p, buried layer terminals 76 a through 76 n, and substrate terminal 78 a through 78 n (or just 78 when a common substrate terminal is used for all cells). Representation of the lines/terminal with letters a-n or a through p, includes not only embodiments which include literally twelve lines/terminals (i.e., a,b,c,d,e,f,g,h,i,j,k,l,m,n,o,p) or fourteen lines/terminals (i.e., a,b,c,d,e,f,g,h,i,j,k,l,m,n,o,p), but is meant to more generically represent a plurality of such line terminals, which can be less than twelve (i.e., as low as one or greater than twelve, thirteen or fourteen (much greater than fourteen up to any positive integer practical).

Each of the source lines 72 a through 72 n is associated with a single row of memory cells 1450 and is coupled to the source line region 16 of each memory cell 1450 in that row. Each of the bit lines 74 a through 74 p is associated with a single column of memory cells 1450 and is coupled to the bit line region 18 of each memory cell 1450 in that column.

Substrate 12 is present at all locations under array 1480. Persons of ordinary skill in the art will appreciate that one or more substrate terminals 78 may be present in one or more locations. Such skilled persons will also appreciate that although array 1480 is shown in FIG. 36 as a single continuous array, many other organizations and layouts are possible. For example, word lines may be segmented or buffered, bit lines may be segmented or buffered, source lines may be segmented or buffered, the array 1480 may be broken into two or more sub-arrays, control circuits such as word decoders, column decoders, segmentation devices, sense amplifiers, write amplifiers may be arrayed around array 1480 or inserted between sub-arrays of array 1480. Thus the present invention is not limited to the exemplary embodiments, features, design options, etc., shown and described.

Several operations can be performed to memory cell 1450, such as: write logic-0, write logic-1, and read. The operation of the memory cell 1450 will be described using an n-channel device as an example.

FIG. 37A is a schematic view of a memory array 1480 showing exemplary bias conditions for performing a write logic-0 operation on the memory array 1480, according to an embodiment of the present invention. FIG. 37B shows exemplary bias conditions applied to a selected memory cell 1450 a during the write logic-0 operation noted with regard to array 1480 in FIG. 37A. The write logic-0 operation corresponds to injecting electrons into the floating gate 60 by a channel hot electron injection mechanism.

The following bias conditions can be applied to the selected memory cell 1450 a for write logic-0 operation as described with reference to FIG. 37B: a positive voltage is applied to the control gate 66 (through WL terminal 70), a positive voltage is applied to the drain region 18 (through BL terminal 74), about zero voltage is applied to the source line region 16 (through SL terminal 72), a positive voltage is applied to the buried layer 22 (through BNL terminal 76), and about zero voltage is applied to the substrate 12 (through substrate terminal 78).

In one particular non-limiting embodiment, about +3.0 volts is applied to WL terminal 70, about +3.0 volts is applied to BL terminal 74, about 0.0 volts is applied to SL terminal 72, about +1.2 volts is applied to BNL terminal 76, and about 0.0 volts is applied to substrate terminal 78.

The positive bias on the control gate 66 (through WL terminal 70) and drain region 18 (through BL terminal 74) will increase the potential of the floating body region 24 through capacitive coupling. Alternatively, the positive bias on the control gate 66 (through the WL terminal 70) and the drain region 18 (through the BL terminal 74) generates electron hole pairs near the junction between the drain region 18 and the floating body region 24 through impact ionization, which injects holes to the floating body region 24 and increases the floating body 24 potential.

When the buried layer 22 (through BNL terminal 76) is positively biased and the potential of the floating body region 24 induced by the capacitive coupling and/or the hole supply due to impact ionization becomes greater than the potential required to turn on the vertical bipolar transistor 30 a, then electrons will flow from the emitter region (source region 16) to the collector region (buried layer 22). If the positive potential applied on the buried layer 22 is sufficient to cause impact ionization, electron hole pairs are generated near a junction between the floating body 24 and the buried layer 22. The impact ionization rate as a function of the electric field is for example described in “Physics of Semiconductor Devices”, Sze S. M. and Ng K. K., which is hereby incorporated herein, in its entirety, by reference thereto.

The generated electrons are collected to the positively biased buried layer 22, while the generated holes flows into the floating body 24. The generated holes become the base current of the lateral bipolar device 30 c and turn the bipolar device 30 c on. As a result, a higher current flows through the cell 1450 (from the BL terminal 74 to the SL terminal 72) compared to when the BNL terminal 76 is grounded. The higher current is a sum of the transistor 20 current and the lateral bipolar device 30 c current. As shown in FIG. 38, the cell 1450 current is boosted higher compared to the cell 1450 current when the BNL terminal 76 is grounded (or at a positive potential not sufficient to cause impact ionization). The electron flow through the cell 1450 (from the SL terminal 72 to the BL terminal 74) then creates electron hole pairs near the junction between the drain region 18 and the floating body region 24. Some of the generated electrons are attracted by the vertical electrical field due to the positive voltage applied to the control gate 66 (through the WL terminal 70), negatively charging the floating gate 60.

The write logic-0 operation (the injection of electrons to the floating gate 60) is enhanced through the application of positive bias to the buried layer 22 (through the BNL terminal 76) due to the higher current flow (from the BL terminal 74 to the SL terminal 72) as shown in FIG. 38. The increased efficiency of the logic-0 operation may be used to increase the speed of the logic-0 operation, or to lower the voltage applied to the drain region 18 and/or the control gate 66, reducing the operating power of the non-volatile memory cell 1450.

If the positive bias applied to the buried layer 22 is too high, the vertical bipolar transistor 30 a and the lateral bipolar transistor 30 c can be turned on even when the gate voltage is zero. In this case, the lateral bipolar transistor 30 c of the unselected cell 1450 c of FIG. 37A is turned on, which results in electron hole pair generation near the junction between the drain region 18 and the floating body region 24 of the unselected cell. The electron-hole pair may cause undesired write ‘0’ to the unselected cell 1450 c. To avoid the undesired write ‘0’, the positive bias applied to the buried layer 22 may be chosen to activate the lateral bipolar transistor of selected cell 1450 a but not activate the lateral bipolar transistor of bit line disturbed cells such as unselected cell 1450 c of FIG. 37A.

FIG. 39 represents the drain 18 voltage and control gate 66 voltage that results in turning on the vertical bipolar device 30 a and enhances the write logic-0 operation. In other words, the lines indicate the minimum control gate 66 voltage and drain 18 voltage to activate the lateral bipolar device 30 c at a given buried layer 22 voltage. The voltages at upper and right region of the line causes the lateral bipolar device 30 c to turn on.

FIG. 40A is a schematic view of a memory array 1480 showing exemplary bias conditions for performing a write logic-1 operation on the memory array 1480, according to an embodiment of the present invention. FIG. 40B shows exemplary bias conditions applied to a selected memory cell 1450 a during the write logic-1 operation noted with regard to array 1480 in FIG. 40A.

The following bias conditions can be applied to memory cell 1450 for a write logic-1 operation as described with reference to FIG. 40B: a negative voltage is applied to the control gate 66 (through WL terminal 70), a positive voltage is applied to the drain region 18 (through BL terminal 74), about zero voltage is applied to the source line region 16 (through SL terminal 72), a positive voltage is applied to the buried layer 22 (through BNL terminal 76), and about zero voltage is applied to the substrate 12 (through substrate terminal 78).

In one particular non-limiting embodiment, about −3.0 volts is applied to WL terminal 70, about +3.0 volts is applied to BL terminal 74, about 0.0 volts is applied to SL terminal 72, about +1.2 volts is applied to BNL terminal 76, and about 0.0 volts is applied to substrate terminal 78.

The negative bias on the control gate 66 (through the WL terminal 70) and the drain region 18 (through the BL terminal 74) causes band-to-band tunneling, which is also referred to as Gate Induced Drain Leakage (GIDL), which injects holes to the floating body region 24 and increases the floating body 24 potential.

When the buried layer 22 (through BNL terminal 76) is positively biased and the potential of the floating body region 24 induced by the hole supply due to GIDL becomes greater than the potential required to turn on the vertical bipolar transistor 30 a, then electrons will flow from the emitter region (source region 16) to the collector region (buried layer 22). If the positive potential applied on the buried layer 22 is sufficient to cause impact ionization, electron hole pairs are generated near a junction between the floating body 24 and the buried layer 22. The generated electrons are collected to the positively biased buried layer 22, while the generated holes flows into the floating body 24. The generated holes become the base current of the lateral bipolar device 30 c and turn the bipolar device 30 c on. As a result, current will flow through the cell 1450 (from the BL terminal 74 to the SL terminal 72). If the lateral bipolar device 30 c is not turned on, there is normally very small current flow from the BL terminal 74 to the SL terminal 72 because of the negative voltage applied to the control gate 66 (through the WL terminal 70). The electron flow through the cell 1450 (from the SL terminal 72 to the BL terminal 74) then creates electron hole pairs near the junction between the drain region 18 and the floating body region 24. Some of the generated holes are then attracted by the vertical electrical field due to the negative voltage applied to the control gate 66 (through the WL terminal 70), positively charging the floating gate 60.

The write logic-1 operation (the injection of holes to the floating gate 60) is enhanced through the application of positive bias to the buried layer 22 (through the BNL terminal 76) due to the activation of the bipolar device 30 c (which in turn is a result of the turning on of the vertical bipolar device 30 a and/or 30 b). The increased efficiency of the logic-1 operation may be used to increase the speed of the logic-1 operation, or to lower the voltage applied to the drain region 18 and/or the control gate 66, reducing the operating power of the non-volatile memory cell 1450. The lowered voltage applied to the control gate 66 can mitigate soft write logic-1 issues in the word line disturbed cell such as the unselected cell 1450 b of FIG. 40A. The write logic-1 operation using hot hole injection mechanism may be used for bit-selective write logic-1 operation.

FIG. 41A is a schematic view of a memory array 1480 showing exemplary bias conditions for performing a read operation on the memory array 1480, according to an embodiment of the present invention. FIG. 41B shows exemplary bias conditions applied to a selected memory cell 1450 a during the read operation noted with regard to array 1480 in FIG. 41A.

FIG. 41B illustrates a read operation applied to the memory cell 1450 a, where the following bias conditions are applied: a positive voltage is applied to the control gate 66 (through the WL terminal 70), a positive voltage lower than the positive voltage applied to the control gate 66 is applied to the drain region 18 during write logic-1 and/or logic-0 operation is applied to the drain region 18 (through the BL terminal 74), zero voltage is applied to the source region 16 (through the SL terminal 72), zero voltage or positive voltage is applied to the buried layer 22 (through the BNL terminal 76), and zero voltage is applied to the substrate terminal 78.

In one particular non-limiting embodiment, about +1.2 volts is applied to WL terminal 70, about +0.4 volts is applied to BL terminal 74, about 0.0 volts is applied to SL terminal 72, about +1.2 volts is applied to BNL terminal 76, and about 0.0 volts is applied to substrate terminal 78.

The charge in the floating gate 60 modulates the current flow through the memory cell 1450 a. FIG. 42 illustrates the drain current-gate voltage (Id-Vg) relationship of the memory cell 1450 in both logic-1 (when the floating gate or trapping layer 60 is positively charged) and logic-0 (when the floating gate or trapping layer 60 is negatively charged). The memory cell 1450 has a lower threshold voltage (gate voltage when the cell 1450 or transistor 20 is turned on) when cell 1450 is in logic-1 state compared to when memory cell 1450 is in logic-0 state. In one embodiment, the voltage applied to the drain region 18 is lower than the voltage required to turn on the lateral bipolar device 30 c to suppress the current flow (from the BL terminal 74 to the SL terminal 72) when the memory cell 1450 is in logic-0 state. In another embodiment, a higher voltage may be applied to the drain region 18 to increase the current flow through the memory cell 1450 (from the BL terminal 74 to the SL terminal 72).

FIG. 43 illustrates a cross-sectional view of another embodiment of memory cell 1550 according to the present invention, which adds a select gate 140 to the memory cell 1450. The select gate 140 is spaced apart from the floating gate or trapping layer 160 (shown as the gap region 168) and is positioned in between the bit line region 118 and the insulating gap region 168, and above the floating body region 124. The select gate 140 is insulated from floating body region 124 by an insulating layer 142. Insulating layer 142 may be made of silicon oxide and/or other dielectric materials, including high-K dielectric materials, such as, but not limited to, tantalum peroxide, titanium oxide, zirconium oxide, hafnium oxide, and/or aluminum oxide. The select gate 140 may be made of, for example, polysilicon material or metal gate electrode, such as tungsten, tantalum, titanium and their nitrides.

In FIG. 43, the source line region 116 is shown to have a larger area than the bit line region 118, which results in a higher coupling ratio between the source line region 116 and the floating gate or trapping layer 160. In another embodiment, the area of the source line region 116 and bit line region 118 may be the same.

Memory cell 1550 includes six terminals: word line (WL) terminal 170, control gate (CG) terminal 180, source line (SL) terminal 172, bit line (BL) terminal 174, buried layer (BNL for buried n-type layer or BPL for buried p-type layer) terminal 176, and substrate terminal 178. Terminal 170 is connected to select gate 140. Terminal 172 is connected to source line region 116 and terminal 174 is connected to bit line region 118. Alternatively, terminal 172 can be connected to bit line region 118 and terminal 174 can be connected to source line region 116. Terminal 176 is connected to buried layer 122. Substrate terminal 178 is connected to substrate 112 below buried layer 122 and terminal 180 is connected to control gate 166. Control gate 166 is positioned above floating gate/trapping layer 160 and insulated therefrom by insulating layer 164 such that floating gate/trapping layer 160 is positioned between insulating layer 162 and surface 14 underlying floating gate/trapping layer 160, and insulating layer 164 and control gate 166 positioned above floating gate/trapping layer 60, as shown. Control gate 66 is capacitively coupled to floating gate/trapping layer 60.

Application of back bias to buried layer 122 (through BNL or BPL terminal 176), which turns on the vertical bipolar devices formed by source line region 116 or bit line region 118, floating body region 124, and buried layer region 122, may be used to enhance the write operations performed to memory cell 1550.

Several operations can be performed to memory cell 1550, such as: write logic-0, write logic-1, and read. The operation of the memory cell 1550 will be described using an n-channel device as an example. The write operations will be described using active low biasing scheme, where the voltage applied to the selected BL terminal 74 a is lower than the voltage applied to the unselected BL terminals (for example 74 b, 74 c, etc.)

The following bias conditions can be applied to the selected memory cell 1550 a for write logic-0 operation as described with reference to FIG. 44: a positive voltage is applied to the select gate 140 (through WL terminal 170), a positive voltage is applied to the control gate 166 (through CG terminal 180), a positive voltage is applied to the source line region 116 (through SL terminal 172), about zero voltage is applied to the bit line region 118 (through BL terminal 174), a positive voltage is applied to the buried layer 122 (through BNL terminal 176), and about zero voltage is applied to the substrate 112 (through substrate terminal 178).

In one particular non-limiting embodiment, about +1.2 volts is applied to the WL terminal 170, about +3.0 volts is applied to CG terminal 180, about +3.0 volts is applied to SL terminal 172, about 0.0 volts is applied to BL terminal 174, about +1.2 volts is applied to BNL terminal 176, and about 0.0 volts is applied to substrate terminal 178.

Similar to cell 1450, the application of a positive bias on the control gate 166 (through CG terminal 180) and source line region 116 (through SL terminal 172) will increase the potential of the floating body region 124 through capacitive coupling and/or the hole supply due to impact ionization. This in turn turns on the bipolar device (formed by the bit line region 118, floating body region 124, and buried layer 122), which subsequently increases the current flow through the cell 1550 (from the SL terminal 172 to the BL terminal 174), compared to when the BNL terminal 176 is grounded. The electron flow from the BL terminal 174 to the SL terminal 172 then creates electron hole pairs near the junction between the source line region 116 and the floating body region 124. Some of the generated electrons are attracted by the vertical electrical field due to the positive voltage applied to the control gate 166 (through the CG terminal 180), which negatively charge the floating gate or trapping layer 160.

FIG. 45 illustrates the bias conditions applied to the selected memory cell 1550 for a write logic-1 operation: a positive voltage is applied to the select gate 140 (through WL terminal 170), a negative voltage is applied to the control gate 166 (through CG terminal 180), a positive voltage is applied to the source line region 116 (through SL terminal 172), about zero voltage is applied to the bit line region 118 (through BL terminal 174), a positive voltage is applied to the buried layer 122 (through BNL terminal 176), and about zero voltage is applied to the substrate 112 (through substrate terminal 178).

In one particular non-limiting embodiment, about +1.2 volts is applied to the WL terminal 170, about −3.0 volts is applied to CG terminal 180, about +3.0 volts is applied to SL terminal 172, about 0.0 volts is applied to BL terminal 174, about +1.2 volts is applied to BNL terminal 176, and about 0.0 volts is applied to substrate terminal 178.

The negative bias on the control gate 166 (through the CG terminal 180) and the positive bias on the source line region 116 (through the SL terminal 172) causes band-to-band tunneling, which is also referred to as Gate Induced Drain Leakage (GIDL), which injects holes to the floating body region 124 and increases the floating body 124 potential. This in turn turns on the bipolar device (formed by the bit line region 118, floating body region 124, and buried layer 122), which subsequently increases the current flow through the cell 1550 (from the SL terminal 172 to the BL terminal 174), compared to when the BNL terminal 176 is grounded. The electron flow from the BL terminal 174 to the SL terminal 172 then creates electron hole pairs near the junction between the source line region 116 and the floating body region 124. Some of the generated holes are attracted by the vertical electrical field due to the negative voltage applied to the control gate 166 (through the CG terminal 180), positively charging the floating gate or trapping layer 160.

FIG. 46 illustrates the bias conditions applied to the selected memory cell 1550 for a read operation: a positive voltage is applied to the select gate 140 (through WL terminal 170), zero or a positive voltage is applied to the control gate 166 (through CG terminal 180), about zero voltage is applied to the source line region 116 (through SL terminal 172), a positive voltage is applied to the bit line region 118 (through BL terminal 174), a positive voltage is applied to the buried layer 122 (through BNL terminal 176), and about zero voltage is applied to the substrate 112 (through substrate terminal 178).

In one particular non-limiting embodiment, about +1.2 volts is applied to the WL terminal 170, about 0.0 volts is applied to CG terminal 180, about 0.0 volts is applied to SL terminal 172, about +0.4 volts is applied to BL terminal 174, about +1.2 volts is applied to BNL terminal 176, and about 0.0 volts is applied to substrate terminal 178.

FIG. 47 illustrates a schematic cross-sectional view of a memory cell 1650 according to another embodiment of the present invention. Memory cell 1650 is similar to memory cell 1550, but where the select gate 140 and control gate 166 (of memory cell 1550) are merged into control gate 266. The select gate 266 may have overlap (partially or complete) with the floating gate or trapping layer 260. The select gate 266 may be made of, for example, polysilicon material or metal gate electrode, such as tungsten, tantalum, titanium and their nitrides.

In FIG. 47, the source line region 216 is shown to have a larger area than the bit line region 218, which results in a higher coupling ratio between the source line region 216 and the floating gate or trapping layer 260. In another embodiment, the area of the source line region 216 and bit line region 218 may be the same.

Memory cell 1650 includes five terminals: word line (WL) terminal 270, source line (SL) terminal 272, bit line (BL) terminal 274, buried layer (BNL for buried n-type layer or BPL for buried p-type layer) terminal 276, and substrate terminal 278. Terminal 170 is connected to select gate 266. Terminal 272 is connected to source line region 216 and terminal 274 is connected to bit line region 218. Alternatively, terminal 272 can be connected to bit line region 218 and terminal 274 can be connected to source line region 216. Terminal 276 is connected to buried layer 222. Substrate terminal 278 is connected to substrate 212 below buried layer 222.

Application to back bias to buried layer 222 (through BNL or BPL terminal 276), which turns on the vertical bipolar devices formed by source line region 216 or bit line region 218, floating body region 224, and buried layer region 222, may be used to enhance the write operations performed to memory cell 1650.

Several operations can be performed to memory cell 1650, such as: write logic-0, write logic-1, and read. The operation of the memory cell 1650 will be described using an n-channel device as an example. The write operations will be described using an active low biasing scheme, where the voltage applied to the selected BL terminal 74 a is lower than the voltage applied to the unselected BL terminals (for example 74 b, 74 c, etc.)

The following bias conditions can be applied to the selected memory cell 1650 for a write logic-0 operation as described with reference to FIG. 48: a positive voltage is applied to the select gate 266 (through WL terminal 270), a positive voltage is applied to the source line region 216 (through SL terminal 272), about zero voltage is applied to the bit line region 218 (through BL terminal 274), a positive voltage is applied to the buried layer 222 (through BNL terminal 276), and about zero voltage is applied to the substrate 212 (through substrate terminal 278).

In one particular non-limiting embodiment, about +3.0 volts is applied to the WL terminal 270, about +3.0 volts is applied to SL terminal 272, about 0.0 volts is applied to BL terminal 274, about +1.2 volts is applied to BNL terminal 276, and about 0.0 volts is applied to substrate terminal 278.

Following the same principles as those of cells 1450 and 1550, the application of a positive bias on the control gate 266 (through WL terminal 270) and source line region 216 (through SL terminal 272) will increase the potential of the floating body region 224 through capacitive coupling and/or the hole supply due to impact ionization. This in turn turns on the bipolar device (formed by the bit line region 218, floating body region 224, and buried layer 222), which subsequently increases the current flow through the cell 1650 (from the SL terminal 272 to the BL terminal 274), compared to when the BNL terminal 276 is grounded. The electron flow from the BL terminal 274 to the SL terminal 272 then creates electron hole pairs near the junction between the source line region 216 and the floating body region 224. Some of the generated electrons are attracted by the vertical electrical field due to the positive voltage applied to the control gate 266 (through the WL terminal 270), negatively charging the floating gate or trapping layer 260.

FIG. 49 illustrates an example of bias conditions applied to the selected memory cell 1650 for write logic-1 operation: a negative voltage is applied to the control gate 266 (through WL terminal 270), a positive voltage is applied to the source line region 216 (through SL terminal 272), about zero voltage is applied to the bit line region 218 (through BL terminal 274), a positive voltage is applied to the buried layer 222 (through BNL terminal 276), and about zero voltage is applied to the substrate 212 (through substrate terminal 278).

In one particular non-limiting embodiment, about −3.0 volts is applied to the WL terminal 270, about +3.0 volts is applied to SL terminal 272, about 0.0 volts is applied to BL terminal 274, about +1.2 volts is applied to BNL terminal 276, and about 0.0 volts is applied to substrate terminal 278.

The negative bias on the control gate 266 (through the WL terminal 270) and the source line region 216 (through the SL terminal 272) causes band-to-band tunneling, which is also referred to as Gate Induced Drain Leakage (GIDL), which injects holes to the floating body region 224 and increases the floating body 224 potential. This in turn turns on the bipolar device (formed by the bit line region 218, floating body region 224, and buried layer 222), which subsequently increases the current flow through the cell 1650 (from the SL terminal 272 to the BL terminal 274), compared to when the BNL terminal 276 is grounded. The electron flow from the BL terminal 274 to the SL terminal 272 then creates electron hole pairs near the junction between the source line region 216 and the floating body region 224. Some of the generated holes are attracted by the vertical electrical field due to the negative voltage applied to the control gate 266 (through the WL terminal 270), positively charging the floating gate or trapping layer 260.

FIG. 50 illustrates an example of bias conditions applied to the selected memory cell 1650 for a read operation: a positive voltage is applied to the control gate 266 (through WL terminal 270), about zero voltage is applied to the source line region 216 (through SL terminal 272), a positive voltage is applied to the bit line region 218 (through BL terminal 274), a positive voltage is applied to the buried layer 222 (through BNL terminal 276), and about zero voltage is applied to the substrate 212 (through substrate terminal 278).

In one particular non-limiting embodiment, about +1.2 volts is applied to the WL terminal 270, about 0.0 volts is applied to SL terminal 272, about +0.4 volts is applied to BL terminal 274, about +1.2 volts is applied to BNL terminal 276, and about 0.0 volts is applied to substrate terminal 278.

FIG. 51 illustrates a schematic cross-sectional view of a memory cell 1750 according to another embodiment of the present invention. Memory cell 1750 is a non-volatile memory cell comprising a resistive change element 41. The resistive change element 41 is shown as a variable resistor, and may be formed from phase change memory material such as a chalcogenide or conductive bridging memory or metal oxide memory, and may take the form of metal-insulator-metal structure, in which transition metal oxide or perovskite metal oxide is used in conjunction with any reasonably good conductors, for example as described in “Overview of Phase-Change Chalcogenide Non-volatile Memory Technology”, S. Hudgens and b. Johnson, MRS Bulletin, vol. 29, issue 11, November 2004, p. 829-832, “Phase Change Memory”, Wong, H.-S. P. et al., Proceedings of the IEEE, vol. 98, no. 12, December 2010, pp. 2201-2227, “Nanoionics-based resistive switching memories”, R. Waser and M. Aono, Nature Materials, vol. 6, November 2007, pp. 833-840, and “Metal-Oxide RRAM”, Wong, H.-S. P. et. al., Proceedings of the IEEE, vol. 100, no. 6, June 2012, pp. 1951-1970, all of which are hereby incorporated herein, in their entireties, by reference thereto. The resistive change element 41 is connected to the source or drain region 16 or 18 of the MOS device 50 having a buried layer 22, typically through a conductive element (for example via and metal used to form semiconductor circuits). MOS device 50 is used as a select device for the resistive change element 41.

The state of the memory cell 1750 is determined by the resistivity of the resistive change element 41. The resistive change element 41 is written (from a low resistivity state to a high resistivity state and vice versa) by flowing an electrical current through the resistive change element 41. In the case of phase change materials, this involves the change of the crystallinity of the chalcogenide materials from crystalline state to amorphous state, while in metal oxide materials, this typically involves the annihilation of conductive filaments.

Similar to memory cells 1450-1650, application of back bias to buried layer 22 of the MOS device 50 may turn on the vertical bipolar devices formed by source region 16 or drain region 18, body region 24, and buried layer 22, and enhance the current flow through the MOS device 50. As a result, the write operations of the memory cell 1750 may be enhanced. The increased efficiency of the write operations may be used to increase the operating speed, or to lower the voltage applied for the write operations, reducing the operating power of the non-volatile memory cell 1750.

A resistive change element 41 oftentimes requires a forming process to be performed prior to the initial operation. The forming operation requires a higher voltage or current. Clearly, it is desired to reduce the voltage or current necessary for the forming process. Application of back bias to buried layer 22 of the MOS device 50 enhances the current flow through the MOS device 50 and therefore increases the efficiency of the forming process, thereby relatively reducing the amount of voltage or current that would otherwise be necessary to perform the forming operation.

From the foregoing it can also be seen that a non-volatile memory cell having reduced operating voltage through the application of a back bias has been described. While the foregoing written description of the invention enables one of ordinary skill to make and use what is considered presently to be the best mode thereof, those of ordinary skill will understand and appreciate the existence of variations, combinations, and equivalents of the specific embodiment, method, and examples herein. The invention should therefore not be limited by the above described embodiment, method, and examples, but by all embodiments and methods within the scope of the invention as claimed. 

1-43. (canceled)
 44. A semiconductor device configured to function as a semiconductor memory device or a transistor with increased on-state drain current, said semiconductor device comprising: a substrate having a first conductivity type selected from p-type conductivity type and n-type conductivity type; a buried layer having a second conductivity type selected from said p-type conductivity type and said n-type conductivity type and being different from said first conductivity type; a body having said first conductivity type; a source region and a drain region each having said second conductivity type and being separated by said body; a gate positioned in between said source region and said drain region; and a select gate spaced apart from said gate.
 45. The semiconductor device of claim 44, wherein said select gate is positioned in between said drain region and said gate, and an insulating gap region is formed between said select gate and said gate.
 46. The semiconductor device of claim 44, wherein said gate is floating and stores non-volatile data in the absence of power.
 47. The semiconductor device of claim 46, wherein applying a voltage to said buried layer region enhances current flow to said gate.
 48. A semiconductor device configured to function as a semiconductor memory device or a transistor with increased on-state drain current, said semiconductor device comprising: a substrate having a first conductivity type selected from p-type conductivity type and n-type conductivity type; a buried layer having a second conductivity type selected from said p-type conductivity type and said n-type conductivity type and being different from said first conductivity type; a body having said first conductivity type; a source region and a drain region each having said second conductivity type and being separated by said body; a gate positioned in between said source region and said drain region; and a control gate spaced apart from said gate.
 49. The semiconductor device of claim 48, wherein said control gate is positioned in between said drain region and said gate, and an insulating gap region is formed between said control gate and said gate.
 50. The semiconductor device of claim 49, wherein said control gate overlaps said insulating gap region and at least partially overlaps said gate.
 51. The semiconductor device of claim 48, wherein said gate is floating and stores non-volatile data in the absence of power.
 52. The semiconductor device of claim 51, wherein applying a voltage to said buried layer region enhances current flow to said gate.
 53. The semiconductor device of claim 48 comprising a fin structure extending from said substrate.
 54. The semiconductor device of claim 44 comprising a fin structure extending from said substrate. 